285 lines
6.5 KiB
C
285 lines
6.5 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell Octeon EP (EndPoint) Ethernet Driver
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*
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* Copyright (C) 2020 Marvell.
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*
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*/
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#ifndef _OCTEP_TX_H_
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#define _OCTEP_TX_H_
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#define IQ_SEND_OK 0
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#define IQ_SEND_STOP 1
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#define IQ_SEND_FAILED -1
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#define TX_BUFTYPE_NONE 0
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#define TX_BUFTYPE_NET 1
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#define TX_BUFTYPE_NET_SG 2
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#define NUM_TX_BUFTYPES 3
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/* Hardware format for Scatter/Gather list */
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struct octep_tx_sglist_desc {
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u16 len[4];
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dma_addr_t dma_ptr[4];
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};
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/* Each Scatter/Gather entry sent to hardwar hold four pointers.
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* So, number of entries required is (MAX_SKB_FRAGS + 1)/4, where '+1'
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* is for main skb which also goes as a gather buffer to Octeon hardware.
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* To allocate sufficient SGLIST entries for a packet with max fragments,
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* align by adding 3 before calcuating max SGLIST entries per packet.
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*/
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#define OCTEP_SGLIST_ENTRIES_PER_PKT ((MAX_SKB_FRAGS + 1 + 3) / 4)
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#define OCTEP_SGLIST_SIZE_PER_PKT \
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(OCTEP_SGLIST_ENTRIES_PER_PKT * sizeof(struct octep_tx_sglist_desc))
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struct octep_tx_buffer {
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struct sk_buff *skb;
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dma_addr_t dma;
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struct octep_tx_sglist_desc *sglist;
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dma_addr_t sglist_dma;
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u8 gather;
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};
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#define OCTEP_IQ_TXBUFF_INFO_SIZE (sizeof(struct octep_tx_buffer))
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/* Hardware interface Tx statistics */
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struct octep_iface_tx_stats {
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/* Packets dropped due to excessive collisions */
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u64 xscol;
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/* Packets dropped due to excessive deferral */
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u64 xsdef;
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/* Packets sent that experienced multiple collisions before successful
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* transmission
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*/
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u64 mcol;
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/* Packets sent that experienced a single collision before successful
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* transmission
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*/
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u64 scol;
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/* Total octets sent on the interface */
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u64 octs;
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/* Total frames sent on the interface */
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u64 pkts;
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/* Packets sent with an octet count < 64 */
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u64 hist_lt64;
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/* Packets sent with an octet count == 64 */
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u64 hist_eq64;
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/* Packets sent with an octet count of 65–127 */
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u64 hist_65to127;
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/* Packets sent with an octet count of 128–255 */
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u64 hist_128to255;
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/* Packets sent with an octet count of 256–511 */
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u64 hist_256to511;
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/* Packets sent with an octet count of 512–1023 */
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u64 hist_512to1023;
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/* Packets sent with an octet count of 1024-1518 */
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u64 hist_1024to1518;
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/* Packets sent with an octet count of > 1518 */
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u64 hist_gt1518;
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/* Packets sent to a broadcast DMAC */
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u64 bcst;
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/* Packets sent to the multicast DMAC */
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u64 mcst;
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/* Packets sent that experienced a transmit underflow and were
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* truncated
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*/
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u64 undflw;
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/* Control/PAUSE packets sent */
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u64 ctl;
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};
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/* Input Queue statistics. Each input queue has four stats fields. */
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struct octep_iq_stats {
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/* Instructions posted to this queue. */
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u64 instr_posted;
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/* Instructions copied by hardware for processing. */
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u64 instr_completed;
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/* Instructions that could not be processed. */
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u64 instr_dropped;
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/* Bytes sent through this queue. */
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u64 bytes_sent;
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/* Gather entries sent through this queue. */
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u64 sgentry_sent;
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/* Number of transmit failures due to TX_BUSY */
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u64 tx_busy;
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/* Number of times the queue is restarted */
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u64 restart_cnt;
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};
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/* The instruction (input) queue.
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* The input queue is used to post raw (instruction) mode data or packet
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* data to Octeon device from the host. Each input queue (up to 4) for
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* a Octeon device has one such structure to represent it.
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*/
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struct octep_iq {
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u32 q_no;
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struct octep_device *octep_dev;
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struct net_device *netdev;
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struct device *dev;
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struct netdev_queue *netdev_q;
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/* Index in input ring where driver should write the next packet */
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u16 host_write_index;
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/* Index in input ring where Octeon is expected to read next packet */
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u16 octep_read_index;
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/* This index aids in finding the window in the queue where Octeon
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* has read the commands.
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*/
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u16 flush_index;
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/* Statistics for this input queue. */
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struct octep_iq_stats stats;
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/* This field keeps track of the instructions pending in this queue. */
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atomic_t instr_pending;
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/* Pointer to the Virtual Base addr of the input ring. */
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struct octep_tx_desc_hw *desc_ring;
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/* DMA mapped base address of the input descriptor ring. */
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dma_addr_t desc_ring_dma;
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/* Info of Tx buffers pending completion. */
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struct octep_tx_buffer *buff_info;
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/* Base pointer to Scatter/Gather lists for all ring descriptors. */
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struct octep_tx_sglist_desc *sglist;
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/* DMA mapped addr of Scatter Gather Lists */
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dma_addr_t sglist_dma;
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/* Octeon doorbell register for the ring. */
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u8 __iomem *doorbell_reg;
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/* Octeon instruction count register for this ring. */
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u8 __iomem *inst_cnt_reg;
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/* interrupt level register for this ring */
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u8 __iomem *intr_lvl_reg;
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/* Maximum no. of instructions in this queue. */
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u32 max_count;
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u32 ring_size_mask;
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u32 pkt_in_done;
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u32 pkts_processed;
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u32 status;
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/* Number of instructions pending to be posted to Octeon. */
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u32 fill_cnt;
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/* The max. number of instructions that can be held pending by the
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* driver before ringing doorbell.
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*/
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u32 fill_threshold;
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};
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/* Hardware Tx Instruction Header */
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struct octep_instr_hdr {
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/* Data Len */
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u64 tlen:16;
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/* Reserved */
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u64 rsvd:20;
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/* PKIND for SDP */
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u64 pkind:6;
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/* Front Data size */
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u64 fsz:6;
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/* No. of entries in gather list */
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u64 gsz:14;
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/* Gather indicator 1=gather*/
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u64 gather:1;
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/* Reserved3 */
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u64 reserved3:1;
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};
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/* Hardware Tx completion response header */
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struct octep_instr_resp_hdr {
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/* Request ID */
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u64 rid:16;
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/* PCIe port to use for response */
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u64 pcie_port:3;
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/* Scatter indicator 1=scatter */
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u64 scatter:1;
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/* Size of Expected result OR no. of entries in scatter list */
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u64 rlenssz:14;
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/* Desired destination port for result */
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u64 dport:6;
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/* Opcode Specific parameters */
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u64 param:8;
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/* Opcode for the return packet */
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u64 opcode:16;
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};
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/* 64-byte Tx instruction format.
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* Format of instruction for a 64-byte mode input queue.
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*
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* only first 16-bytes (dptr and ih) are mandatory; rest are optional
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* and filled by the driver based on firmware/hardware capabilities.
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* These optional headers together called Front Data and its size is
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* described by ih->fsz.
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*/
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struct octep_tx_desc_hw {
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/* Pointer where the input data is available. */
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u64 dptr;
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/* Instruction Header. */
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union {
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struct octep_instr_hdr ih;
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u64 ih64;
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};
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/* Pointer where the response for a RAW mode packet will be written
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* by Octeon.
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*/
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u64 rptr;
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/* Input Instruction Response Header. */
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struct octep_instr_resp_hdr irh;
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/* Additional headers available in a 64-byte instruction. */
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u64 exhdr[4];
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};
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#define OCTEP_IQ_DESC_SIZE (sizeof(struct octep_tx_desc_hw))
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#endif /* _OCTEP_TX_H_ */
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