417 lines
9.8 KiB
C
417 lines
9.8 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/* Marvell RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell.
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*
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*/
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#include <linux/module.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include "rvu_reg.h"
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#include "mbox.h"
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#include "rvu_trace.h"
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static const u16 msgs_offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);
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void __otx2_mbox_reset(struct otx2_mbox *mbox, int devid)
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{
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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struct mbox_hdr *tx_hdr, *rx_hdr;
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void *hw_mbase = mdev->hwbase;
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tx_hdr = hw_mbase + mbox->tx_start;
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rx_hdr = hw_mbase + mbox->rx_start;
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mdev->msg_size = 0;
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mdev->rsp_size = 0;
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tx_hdr->num_msgs = 0;
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tx_hdr->msg_size = 0;
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rx_hdr->num_msgs = 0;
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rx_hdr->msg_size = 0;
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}
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EXPORT_SYMBOL(__otx2_mbox_reset);
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void otx2_mbox_reset(struct otx2_mbox *mbox, int devid)
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{
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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spin_lock(&mdev->mbox_lock);
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__otx2_mbox_reset(mbox, devid);
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spin_unlock(&mdev->mbox_lock);
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}
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EXPORT_SYMBOL(otx2_mbox_reset);
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void otx2_mbox_destroy(struct otx2_mbox *mbox)
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{
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mbox->reg_base = NULL;
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mbox->hwbase = NULL;
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kfree(mbox->dev);
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mbox->dev = NULL;
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}
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EXPORT_SYMBOL(otx2_mbox_destroy);
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static int otx2_mbox_setup(struct otx2_mbox *mbox, struct pci_dev *pdev,
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void *reg_base, int direction, int ndevs)
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{
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switch (direction) {
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case MBOX_DIR_AFPF:
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case MBOX_DIR_PFVF:
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mbox->tx_start = MBOX_DOWN_TX_START;
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mbox->rx_start = MBOX_DOWN_RX_START;
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mbox->tx_size = MBOX_DOWN_TX_SIZE;
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mbox->rx_size = MBOX_DOWN_RX_SIZE;
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break;
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case MBOX_DIR_PFAF:
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case MBOX_DIR_VFPF:
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mbox->tx_start = MBOX_DOWN_RX_START;
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mbox->rx_start = MBOX_DOWN_TX_START;
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mbox->tx_size = MBOX_DOWN_RX_SIZE;
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mbox->rx_size = MBOX_DOWN_TX_SIZE;
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break;
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case MBOX_DIR_AFPF_UP:
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case MBOX_DIR_PFVF_UP:
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mbox->tx_start = MBOX_UP_TX_START;
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mbox->rx_start = MBOX_UP_RX_START;
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mbox->tx_size = MBOX_UP_TX_SIZE;
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mbox->rx_size = MBOX_UP_RX_SIZE;
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break;
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case MBOX_DIR_PFAF_UP:
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case MBOX_DIR_VFPF_UP:
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mbox->tx_start = MBOX_UP_RX_START;
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mbox->rx_start = MBOX_UP_TX_START;
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mbox->tx_size = MBOX_UP_RX_SIZE;
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mbox->rx_size = MBOX_UP_TX_SIZE;
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break;
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default:
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return -ENODEV;
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}
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switch (direction) {
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case MBOX_DIR_AFPF:
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case MBOX_DIR_AFPF_UP:
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mbox->trigger = RVU_AF_AFPF_MBOX0;
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mbox->tr_shift = 4;
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break;
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case MBOX_DIR_PFAF:
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case MBOX_DIR_PFAF_UP:
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mbox->trigger = RVU_PF_PFAF_MBOX1;
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mbox->tr_shift = 0;
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break;
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case MBOX_DIR_PFVF:
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case MBOX_DIR_PFVF_UP:
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mbox->trigger = RVU_PF_VFX_PFVF_MBOX0;
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mbox->tr_shift = 12;
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break;
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case MBOX_DIR_VFPF:
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case MBOX_DIR_VFPF_UP:
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mbox->trigger = RVU_VF_VFPF_MBOX1;
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mbox->tr_shift = 0;
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break;
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default:
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return -ENODEV;
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}
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mbox->reg_base = reg_base;
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mbox->pdev = pdev;
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mbox->dev = kcalloc(ndevs, sizeof(struct otx2_mbox_dev), GFP_KERNEL);
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if (!mbox->dev) {
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otx2_mbox_destroy(mbox);
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return -ENOMEM;
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}
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mbox->ndevs = ndevs;
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return 0;
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}
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int otx2_mbox_init(struct otx2_mbox *mbox, void *hwbase, struct pci_dev *pdev,
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void *reg_base, int direction, int ndevs)
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{
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struct otx2_mbox_dev *mdev;
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int devid, err;
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err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
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if (err)
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return err;
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mbox->hwbase = hwbase;
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for (devid = 0; devid < ndevs; devid++) {
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mdev = &mbox->dev[devid];
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mdev->mbase = mbox->hwbase + (devid * MBOX_SIZE);
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mdev->hwbase = mdev->mbase;
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spin_lock_init(&mdev->mbox_lock);
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/* Init header to reset value */
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otx2_mbox_reset(mbox, devid);
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}
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return 0;
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}
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EXPORT_SYMBOL(otx2_mbox_init);
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/* Initialize mailbox with the set of mailbox region addresses
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* in the array hwbase.
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*/
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int otx2_mbox_regions_init(struct otx2_mbox *mbox, void **hwbase,
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struct pci_dev *pdev, void *reg_base,
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int direction, int ndevs, unsigned long *pf_bmap)
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{
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struct otx2_mbox_dev *mdev;
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int devid, err;
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err = otx2_mbox_setup(mbox, pdev, reg_base, direction, ndevs);
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if (err)
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return err;
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mbox->hwbase = hwbase[0];
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for (devid = 0; devid < ndevs; devid++) {
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if (!test_bit(devid, pf_bmap))
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continue;
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mdev = &mbox->dev[devid];
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mdev->mbase = hwbase[devid];
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mdev->hwbase = hwbase[devid];
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spin_lock_init(&mdev->mbox_lock);
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/* Init header to reset value */
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otx2_mbox_reset(mbox, devid);
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}
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return 0;
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}
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EXPORT_SYMBOL(otx2_mbox_regions_init);
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int otx2_mbox_wait_for_rsp(struct otx2_mbox *mbox, int devid)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(MBOX_RSP_TIMEOUT);
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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struct device *sender = &mbox->pdev->dev;
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while (!time_after(jiffies, timeout)) {
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if (mdev->num_msgs == mdev->msgs_acked)
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return 0;
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usleep_range(800, 1000);
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}
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dev_dbg(sender, "timed out while waiting for rsp\n");
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return -EIO;
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}
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EXPORT_SYMBOL(otx2_mbox_wait_for_rsp);
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int otx2_mbox_busy_poll_for_rsp(struct otx2_mbox *mbox, int devid)
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{
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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unsigned long timeout = jiffies + 1 * HZ;
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while (!time_after(jiffies, timeout)) {
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if (mdev->num_msgs == mdev->msgs_acked)
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return 0;
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cpu_relax();
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}
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return -EIO;
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}
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EXPORT_SYMBOL(otx2_mbox_busy_poll_for_rsp);
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void otx2_mbox_msg_send(struct otx2_mbox *mbox, int devid)
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{
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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struct mbox_hdr *tx_hdr, *rx_hdr;
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void *hw_mbase = mdev->hwbase;
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tx_hdr = hw_mbase + mbox->tx_start;
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rx_hdr = hw_mbase + mbox->rx_start;
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/* If bounce buffer is implemented copy mbox messages from
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* bounce buffer to hw mbox memory.
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*/
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if (mdev->mbase != hw_mbase)
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memcpy(hw_mbase + mbox->tx_start + msgs_offset,
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mdev->mbase + mbox->tx_start + msgs_offset,
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mdev->msg_size);
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spin_lock(&mdev->mbox_lock);
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tx_hdr->msg_size = mdev->msg_size;
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/* Reset header for next messages */
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mdev->msg_size = 0;
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mdev->rsp_size = 0;
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mdev->msgs_acked = 0;
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/* Sync mbox data into memory */
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smp_wmb();
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/* num_msgs != 0 signals to the peer that the buffer has a number of
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* messages. So this should be written after writing all the messages
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* to the shared memory.
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*/
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tx_hdr->num_msgs = mdev->num_msgs;
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rx_hdr->num_msgs = 0;
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trace_otx2_msg_send(mbox->pdev, tx_hdr->num_msgs, tx_hdr->msg_size);
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spin_unlock(&mdev->mbox_lock);
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/* The interrupt should be fired after num_msgs is written
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* to the shared memory
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*/
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writeq(1, (void __iomem *)mbox->reg_base +
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(mbox->trigger | (devid << mbox->tr_shift)));
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}
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EXPORT_SYMBOL(otx2_mbox_msg_send);
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struct mbox_msghdr *otx2_mbox_alloc_msg_rsp(struct otx2_mbox *mbox, int devid,
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int size, int size_rsp)
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{
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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struct mbox_msghdr *msghdr = NULL;
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spin_lock(&mdev->mbox_lock);
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size = ALIGN(size, MBOX_MSG_ALIGN);
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size_rsp = ALIGN(size_rsp, MBOX_MSG_ALIGN);
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/* Check if there is space in mailbox */
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if ((mdev->msg_size + size) > mbox->tx_size - msgs_offset)
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goto exit;
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if ((mdev->rsp_size + size_rsp) > mbox->rx_size - msgs_offset)
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goto exit;
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if (mdev->msg_size == 0)
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mdev->num_msgs = 0;
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mdev->num_msgs++;
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msghdr = mdev->mbase + mbox->tx_start + msgs_offset + mdev->msg_size;
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/* Clear the whole msg region */
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memset(msghdr, 0, size);
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/* Init message header with reset values */
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msghdr->ver = OTX2_MBOX_VERSION;
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mdev->msg_size += size;
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mdev->rsp_size += size_rsp;
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msghdr->next_msgoff = mdev->msg_size + msgs_offset;
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exit:
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spin_unlock(&mdev->mbox_lock);
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return msghdr;
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}
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EXPORT_SYMBOL(otx2_mbox_alloc_msg_rsp);
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struct mbox_msghdr *otx2_mbox_get_rsp(struct otx2_mbox *mbox, int devid,
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struct mbox_msghdr *msg)
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{
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unsigned long imsg = mbox->tx_start + msgs_offset;
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unsigned long irsp = mbox->rx_start + msgs_offset;
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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u16 msgs;
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spin_lock(&mdev->mbox_lock);
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if (mdev->num_msgs != mdev->msgs_acked)
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goto error;
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for (msgs = 0; msgs < mdev->msgs_acked; msgs++) {
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struct mbox_msghdr *pmsg = mdev->mbase + imsg;
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struct mbox_msghdr *prsp = mdev->mbase + irsp;
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if (msg == pmsg) {
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if (pmsg->id != prsp->id)
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goto error;
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spin_unlock(&mdev->mbox_lock);
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return prsp;
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}
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imsg = mbox->tx_start + pmsg->next_msgoff;
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irsp = mbox->rx_start + prsp->next_msgoff;
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}
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error:
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spin_unlock(&mdev->mbox_lock);
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return ERR_PTR(-ENODEV);
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}
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EXPORT_SYMBOL(otx2_mbox_get_rsp);
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int otx2_mbox_check_rsp_msgs(struct otx2_mbox *mbox, int devid)
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{
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unsigned long ireq = mbox->tx_start + msgs_offset;
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unsigned long irsp = mbox->rx_start + msgs_offset;
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struct otx2_mbox_dev *mdev = &mbox->dev[devid];
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int rc = -ENODEV;
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u16 msgs;
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spin_lock(&mdev->mbox_lock);
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if (mdev->num_msgs != mdev->msgs_acked)
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goto exit;
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for (msgs = 0; msgs < mdev->msgs_acked; msgs++) {
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struct mbox_msghdr *preq = mdev->mbase + ireq;
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struct mbox_msghdr *prsp = mdev->mbase + irsp;
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if (preq->id != prsp->id) {
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trace_otx2_msg_check(mbox->pdev, preq->id,
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prsp->id, prsp->rc);
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goto exit;
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}
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if (prsp->rc) {
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rc = prsp->rc;
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trace_otx2_msg_check(mbox->pdev, preq->id,
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||
|
|
prsp->id, prsp->rc);
|
||
|
|
goto exit;
|
||
|
|
}
|
||
|
|
|
||
|
|
ireq = mbox->tx_start + preq->next_msgoff;
|
||
|
|
irsp = mbox->rx_start + prsp->next_msgoff;
|
||
|
|
}
|
||
|
|
rc = 0;
|
||
|
|
exit:
|
||
|
|
spin_unlock(&mdev->mbox_lock);
|
||
|
|
return rc;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(otx2_mbox_check_rsp_msgs);
|
||
|
|
|
||
|
|
int
|
||
|
|
otx2_reply_invalid_msg(struct otx2_mbox *mbox, int devid, u16 pcifunc, u16 id)
|
||
|
|
{
|
||
|
|
struct msg_rsp *rsp;
|
||
|
|
|
||
|
|
rsp = (struct msg_rsp *)
|
||
|
|
otx2_mbox_alloc_msg(mbox, devid, sizeof(*rsp));
|
||
|
|
if (!rsp)
|
||
|
|
return -ENOMEM;
|
||
|
|
rsp->hdr.id = id;
|
||
|
|
rsp->hdr.sig = OTX2_MBOX_RSP_SIG;
|
||
|
|
rsp->hdr.rc = MBOX_MSG_INVALID;
|
||
|
|
rsp->hdr.pcifunc = pcifunc;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(otx2_reply_invalid_msg);
|
||
|
|
|
||
|
|
bool otx2_mbox_nonempty(struct otx2_mbox *mbox, int devid)
|
||
|
|
{
|
||
|
|
struct otx2_mbox_dev *mdev = &mbox->dev[devid];
|
||
|
|
bool ret;
|
||
|
|
|
||
|
|
spin_lock(&mdev->mbox_lock);
|
||
|
|
ret = mdev->num_msgs != 0;
|
||
|
|
spin_unlock(&mdev->mbox_lock);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(otx2_mbox_nonempty);
|
||
|
|
|
||
|
|
const char *otx2_mbox_id2name(u16 id)
|
||
|
|
{
|
||
|
|
switch (id) {
|
||
|
|
#define M(_name, _id, _1, _2, _3) case _id: return # _name;
|
||
|
|
MBOX_MESSAGES
|
||
|
|
#undef M
|
||
|
|
default:
|
||
|
|
return "INVALID ID";
|
||
|
|
}
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(otx2_mbox_id2name);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Marvell.");
|
||
|
|
MODULE_LICENSE("GPL v2");
|