132 lines
4.4 KiB
C
132 lines
4.4 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
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/* Copyright(c) 2020 Intel Corporation. All rights reserved. */
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#ifndef _NTB_INTEL_GEN4_H_
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#define _NTB_INTEL_GEN4_H_
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#include "ntb_hw_intel.h"
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/* Supported PCI device revision range for ICX */
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#define PCI_DEVICE_REVISION_ICX_MIN 0x2
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#define PCI_DEVICE_REVISION_ICX_MAX 0xF
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/* Intel Gen4 NTB hardware */
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/* PCIe config space */
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#define GEN4_IMBAR23SZ_OFFSET 0x00c4
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#define GEN4_IMBAR45SZ_OFFSET 0x00c5
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#define GEN4_EMBAR23SZ_OFFSET 0x00c6
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#define GEN4_EMBAR45SZ_OFFSET 0x00c7
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#define GEN4_DEVCTRL_OFFSET 0x0048
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#define GEN4_DEVSTS_OFFSET 0x004a
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#define GEN4_UNCERRSTS_OFFSET 0x0104
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#define GEN4_CORERRSTS_OFFSET 0x0110
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/* BAR0 MMIO */
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#define GEN4_NTBCNTL_OFFSET 0x0000
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#define GEN4_IM23XBASE_OFFSET 0x0010 /* IMBAR1XBASE */
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#define GEN4_IM23XLMT_OFFSET 0x0018 /* IMBAR1XLMT */
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#define GEN4_IM45XBASE_OFFSET 0x0020 /* IMBAR2XBASE */
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#define GEN4_IM45XLMT_OFFSET 0x0028 /* IMBAR2XLMT */
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#define GEN4_IM_INT_STATUS_OFFSET 0x0040
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#define GEN4_IM_INT_DISABLE_OFFSET 0x0048
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#define GEN4_INTVEC_OFFSET 0x0050 /* 0-32 vecs */
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#define GEN4_IM23XBASEIDX_OFFSET 0x0074
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#define GEN4_IM45XBASEIDX_OFFSET 0x0076
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#define GEN4_IM_SPAD_OFFSET 0x0080 /* 0-15 SPADs */
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#define GEN4_IM_SPAD_SEM_OFFSET 0x00c0 /* SPAD hw semaphore */
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#define GEN4_IM_SPAD_STICKY_OFFSET 0x00c4 /* sticky SPAD */
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#define GEN4_IM_DOORBELL_OFFSET 0x0100 /* 0-31 doorbells */
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#define GEN4_LTR_SWSEL_OFFSET 0x30ec
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#define GEN4_LTR_ACTIVE_OFFSET 0x30f0
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#define GEN4_LTR_IDLE_OFFSET 0x30f4
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#define GEN4_EM_SPAD_OFFSET 0x8080
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/* note, link status is now in MMIO and not config space for NTB */
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#define GEN4_LINK_CTRL_OFFSET 0xb050
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#define GEN4_LINK_STATUS_OFFSET 0xb052
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#define GEN4_PPD0_OFFSET 0xb0d4
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#define GEN4_PPD1_OFFSET 0xb4c0
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#define GEN4_LTSSMSTATEJMP 0xf040
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#define GEN4_PPD_CLEAR_TRN 0x0001
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#define GEN4_PPD_LINKTRN 0x0008
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#define GEN4_PPD_CONN_MASK 0x0300
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#define SPR_PPD_CONN_MASK 0x0700
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#define GEN4_PPD_CONN_B2B 0x0200
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#define GEN4_PPD_DEV_MASK 0x1000
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#define GEN4_PPD_DEV_DSD 0x1000
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#define GEN4_PPD_DEV_USD 0x0000
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#define SPR_PPD_DEV_MASK 0x4000
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#define SPR_PPD_DEV_DSD 0x4000
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#define SPR_PPD_DEV_USD 0x0000
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#define GEN4_LINK_CTRL_LINK_DISABLE 0x0010
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#define GEN4_SLOTSTS 0xb05a
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#define GEN4_SLOTSTS_DLLSCS 0x100
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#define GEN4_PPD_TOPO_MASK (GEN4_PPD_CONN_MASK | GEN4_PPD_DEV_MASK)
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#define GEN4_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_USD)
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#define GEN4_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | GEN4_PPD_DEV_DSD)
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#define SPR_PPD_TOPO_MASK (SPR_PPD_CONN_MASK | SPR_PPD_DEV_MASK)
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#define SPR_PPD_TOPO_B2B_USD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_USD)
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#define SPR_PPD_TOPO_B2B_DSD (GEN4_PPD_CONN_B2B | SPR_PPD_DEV_DSD)
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#define GEN4_DB_COUNT 32
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#define GEN4_DB_LINK 32
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#define GEN4_DB_LINK_BIT BIT_ULL(GEN4_DB_LINK)
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#define GEN4_DB_MSIX_VECTOR_COUNT 33
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#define GEN4_DB_MSIX_VECTOR_SHIFT 1
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#define GEN4_DB_TOTAL_SHIFT 33
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#define GEN4_SPAD_COUNT 16
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#define NTB_CTL_E2I_BAR23_SNOOP 0x000004
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#define NTB_CTL_E2I_BAR23_NOSNOOP 0x000008
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#define NTB_CTL_I2E_BAR23_SNOOP 0x000010
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#define NTB_CTL_I2E_BAR23_NOSNOOP 0x000020
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#define NTB_CTL_E2I_BAR45_SNOOP 0x000040
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#define NTB_CTL_E2I_BAR45_NOSNOO 0x000080
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#define NTB_CTL_I2E_BAR45_SNOOP 0x000100
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#define NTB_CTL_I2E_BAR45_NOSNOOP 0x000200
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#define NTB_CTL_BUSNO_DIS_INC 0x000400
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#define NTB_CTL_LINK_DOWN 0x010000
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#define NTB_SJC_FORCEDETECT 0x000004
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#define NTB_LTR_SWSEL_ACTIVE 0x0
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#define NTB_LTR_SWSEL_IDLE 0x1
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#define NTB_LTR_NS_SHIFT 16
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#define NTB_LTR_ACTIVE_VAL 0x0000 /* 0 us */
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#define NTB_LTR_ACTIVE_LATSCALE 0x0800 /* 1us scale */
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#define NTB_LTR_ACTIVE_REQMNT 0x8000 /* snoop req enable */
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#define NTB_LTR_IDLE_VAL 0x0258 /* 600 us */
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#define NTB_LTR_IDLE_LATSCALE 0x0800 /* 1us scale */
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#define NTB_LTR_IDLE_REQMNT 0x8000 /* snoop req enable */
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ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
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size_t count, loff_t *offp);
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int gen4_init_dev(struct intel_ntb_dev *ndev);
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ssize_t ndev_ntb4_debugfs_read(struct file *filp, char __user *ubuf,
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size_t count, loff_t *offp);
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extern const struct ntb_dev_ops intel_ntb4_ops;
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static inline int pdev_is_ICX(struct pci_dev *pdev)
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{
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if (pdev_is_gen4(pdev) &&
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pdev->revision >= PCI_DEVICE_REVISION_ICX_MIN &&
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pdev->revision <= PCI_DEVICE_REVISION_ICX_MAX)
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return 1;
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return 0;
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}
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static inline int pdev_is_SPR(struct pci_dev *pdev)
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{
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if (pdev_is_gen4(pdev) &&
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pdev->revision > PCI_DEVICE_REVISION_ICX_MAX)
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return 1;
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return 0;
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}
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#endif
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