622 lines
16 KiB
C
622 lines
16 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCIe host controller driver for Xilinx AXI PCIe Bridge
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*
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* Copyright (c) 2012 - 2014 Xilinx, Inc.
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*
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* Based on the Tegra PCIe driver
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*
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* Bits taken from Synopsys DesignWare Host controller driver and
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* ARM PCI Host generic driver.
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*/
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/irqdomain.h>
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/msi.h>
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#include <linux/of_address.h>
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#include <linux/of_pci.h>
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#include <linux/of_platform.h>
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#include <linux/of_irq.h>
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#include <linux/pci.h>
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#include <linux/pci-ecam.h>
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#include <linux/platform_device.h>
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#include "../pci.h"
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/* Register definitions */
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#define XILINX_PCIE_REG_BIR 0x00000130
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#define XILINX_PCIE_REG_IDR 0x00000138
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#define XILINX_PCIE_REG_IMR 0x0000013c
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#define XILINX_PCIE_REG_PSCR 0x00000144
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#define XILINX_PCIE_REG_RPSC 0x00000148
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#define XILINX_PCIE_REG_MSIBASE1 0x0000014c
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#define XILINX_PCIE_REG_MSIBASE2 0x00000150
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#define XILINX_PCIE_REG_RPEFR 0x00000154
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#define XILINX_PCIE_REG_RPIFR1 0x00000158
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#define XILINX_PCIE_REG_RPIFR2 0x0000015c
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/* Interrupt registers definitions */
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#define XILINX_PCIE_INTR_LINK_DOWN BIT(0)
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#define XILINX_PCIE_INTR_ECRC_ERR BIT(1)
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#define XILINX_PCIE_INTR_STR_ERR BIT(2)
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#define XILINX_PCIE_INTR_HOT_RESET BIT(3)
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#define XILINX_PCIE_INTR_CFG_TIMEOUT BIT(8)
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#define XILINX_PCIE_INTR_CORRECTABLE BIT(9)
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#define XILINX_PCIE_INTR_NONFATAL BIT(10)
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#define XILINX_PCIE_INTR_FATAL BIT(11)
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#define XILINX_PCIE_INTR_INTX BIT(16)
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#define XILINX_PCIE_INTR_MSI BIT(17)
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#define XILINX_PCIE_INTR_SLV_UNSUPP BIT(20)
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#define XILINX_PCIE_INTR_SLV_UNEXP BIT(21)
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#define XILINX_PCIE_INTR_SLV_COMPL BIT(22)
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#define XILINX_PCIE_INTR_SLV_ERRP BIT(23)
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#define XILINX_PCIE_INTR_SLV_CMPABT BIT(24)
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#define XILINX_PCIE_INTR_SLV_ILLBUR BIT(25)
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#define XILINX_PCIE_INTR_MST_DECERR BIT(26)
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#define XILINX_PCIE_INTR_MST_SLVERR BIT(27)
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#define XILINX_PCIE_INTR_MST_ERRP BIT(28)
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#define XILINX_PCIE_IMR_ALL_MASK 0x1FF30FED
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#define XILINX_PCIE_IMR_ENABLE_MASK 0x1FF30F0D
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#define XILINX_PCIE_IDR_ALL_MASK 0xFFFFFFFF
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/* Root Port Error FIFO Read Register definitions */
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#define XILINX_PCIE_RPEFR_ERR_VALID BIT(18)
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#define XILINX_PCIE_RPEFR_REQ_ID GENMASK(15, 0)
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#define XILINX_PCIE_RPEFR_ALL_MASK 0xFFFFFFFF
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/* Root Port Interrupt FIFO Read Register 1 definitions */
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#define XILINX_PCIE_RPIFR1_INTR_VALID BIT(31)
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#define XILINX_PCIE_RPIFR1_MSI_INTR BIT(30)
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#define XILINX_PCIE_RPIFR1_INTR_MASK GENMASK(28, 27)
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#define XILINX_PCIE_RPIFR1_ALL_MASK 0xFFFFFFFF
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#define XILINX_PCIE_RPIFR1_INTR_SHIFT 27
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/* Bridge Info Register definitions */
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#define XILINX_PCIE_BIR_ECAM_SZ_MASK GENMASK(18, 16)
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#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT 16
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/* Root Port Interrupt FIFO Read Register 2 definitions */
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#define XILINX_PCIE_RPIFR2_MSG_DATA GENMASK(15, 0)
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/* Root Port Status/control Register definitions */
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#define XILINX_PCIE_REG_RPSC_BEN BIT(0)
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/* Phy Status/Control Register definitions */
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#define XILINX_PCIE_REG_PSCR_LNKUP BIT(11)
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/* Number of MSI IRQs */
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#define XILINX_NUM_MSI_IRQS 128
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/**
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* struct xilinx_pcie - PCIe port information
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* @dev: Device pointer
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* @reg_base: IO Mapped Register Base
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* @msi_map: Bitmap of allocated MSIs
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* @map_lock: Mutex protecting the MSI allocation
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* @msi_domain: MSI IRQ domain pointer
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* @leg_domain: Legacy IRQ domain pointer
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* @resources: Bus Resources
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*/
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struct xilinx_pcie {
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struct device *dev;
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void __iomem *reg_base;
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unsigned long msi_map[BITS_TO_LONGS(XILINX_NUM_MSI_IRQS)];
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struct mutex map_lock;
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struct irq_domain *msi_domain;
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struct irq_domain *leg_domain;
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struct list_head resources;
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};
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static inline u32 pcie_read(struct xilinx_pcie *pcie, u32 reg)
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{
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return readl(pcie->reg_base + reg);
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}
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static inline void pcie_write(struct xilinx_pcie *pcie, u32 val, u32 reg)
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{
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writel(val, pcie->reg_base + reg);
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}
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static inline bool xilinx_pcie_link_up(struct xilinx_pcie *pcie)
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{
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return (pcie_read(pcie, XILINX_PCIE_REG_PSCR) &
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XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
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}
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/**
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* xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
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* @pcie: PCIe port information
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*/
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static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie *pcie)
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{
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struct device *dev = pcie->dev;
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unsigned long val = pcie_read(pcie, XILINX_PCIE_REG_RPEFR);
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if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
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dev_dbg(dev, "Requester ID %lu\n",
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val & XILINX_PCIE_RPEFR_REQ_ID);
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pcie_write(pcie, XILINX_PCIE_RPEFR_ALL_MASK,
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XILINX_PCIE_REG_RPEFR);
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}
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}
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/**
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* xilinx_pcie_valid_device - Check if a valid device is present on bus
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* @bus: PCI Bus structure
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* @devfn: device/function
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*
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* Return: 'true' on success and 'false' if invalid device is found
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*/
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static bool xilinx_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
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{
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struct xilinx_pcie *pcie = bus->sysdata;
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/* Check if link is up when trying to access downstream pcie ports */
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if (!pci_is_root_bus(bus)) {
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if (!xilinx_pcie_link_up(pcie))
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return false;
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} else if (devfn > 0) {
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/* Only one device down on each root port */
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return false;
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}
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return true;
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}
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/**
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* xilinx_pcie_map_bus - Get configuration base
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* @bus: PCI Bus structure
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* @devfn: Device/function
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* @where: Offset from base
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*
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* Return: Base address of the configuration space needed to be
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* accessed.
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*/
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static void __iomem *xilinx_pcie_map_bus(struct pci_bus *bus,
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unsigned int devfn, int where)
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{
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struct xilinx_pcie *pcie = bus->sysdata;
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if (!xilinx_pcie_valid_device(bus, devfn))
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return NULL;
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return pcie->reg_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
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}
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/* PCIe operations */
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static struct pci_ops xilinx_pcie_ops = {
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.map_bus = xilinx_pcie_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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};
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/* MSI functions */
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static void xilinx_msi_top_irq_ack(struct irq_data *d)
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{
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/*
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* xilinx_pcie_intr_handler() will have performed the Ack.
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* Eventually, this should be fixed and the Ack be moved in
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* the respective callbacks for INTx and MSI.
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*/
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}
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static struct irq_chip xilinx_msi_top_chip = {
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.name = "PCIe MSI",
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.irq_ack = xilinx_msi_top_irq_ack,
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};
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static int xilinx_msi_set_affinity(struct irq_data *d, const struct cpumask *mask, bool force)
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{
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return -EINVAL;
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}
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static void xilinx_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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{
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struct xilinx_pcie *pcie = irq_data_get_irq_chip_data(data);
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phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);
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msg->address_lo = lower_32_bits(pa);
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msg->address_hi = upper_32_bits(pa);
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msg->data = data->hwirq;
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}
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static struct irq_chip xilinx_msi_bottom_chip = {
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.name = "Xilinx MSI",
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.irq_set_affinity = xilinx_msi_set_affinity,
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.irq_compose_msi_msg = xilinx_compose_msi_msg,
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};
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static int xilinx_msi_domain_alloc(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs, void *args)
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{
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struct xilinx_pcie *pcie = domain->host_data;
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int hwirq, i;
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mutex_lock(&pcie->map_lock);
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hwirq = bitmap_find_free_region(pcie->msi_map, XILINX_NUM_MSI_IRQS, order_base_2(nr_irqs));
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mutex_unlock(&pcie->map_lock);
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if (hwirq < 0)
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return -ENOSPC;
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for (i = 0; i < nr_irqs; i++)
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irq_domain_set_info(domain, virq + i, hwirq + i,
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&xilinx_msi_bottom_chip, domain->host_data,
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handle_edge_irq, NULL, NULL);
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return 0;
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}
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static void xilinx_msi_domain_free(struct irq_domain *domain, unsigned int virq,
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unsigned int nr_irqs)
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{
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struct irq_data *d = irq_domain_get_irq_data(domain, virq);
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struct xilinx_pcie *pcie = domain->host_data;
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mutex_lock(&pcie->map_lock);
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bitmap_release_region(pcie->msi_map, d->hwirq, order_base_2(nr_irqs));
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mutex_unlock(&pcie->map_lock);
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}
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static const struct irq_domain_ops xilinx_msi_domain_ops = {
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.alloc = xilinx_msi_domain_alloc,
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.free = xilinx_msi_domain_free,
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};
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static struct msi_domain_info xilinx_msi_info = {
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
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.chip = &xilinx_msi_top_chip,
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};
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static int xilinx_allocate_msi_domains(struct xilinx_pcie *pcie)
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{
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struct fwnode_handle *fwnode = dev_fwnode(pcie->dev);
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struct irq_domain *parent;
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parent = irq_domain_create_linear(fwnode, XILINX_NUM_MSI_IRQS,
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&xilinx_msi_domain_ops, pcie);
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if (!parent) {
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dev_err(pcie->dev, "failed to create IRQ domain\n");
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return -ENOMEM;
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}
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irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS);
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pcie->msi_domain = pci_msi_create_irq_domain(fwnode, &xilinx_msi_info, parent);
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if (!pcie->msi_domain) {
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dev_err(pcie->dev, "failed to create MSI domain\n");
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irq_domain_remove(parent);
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return -ENOMEM;
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}
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return 0;
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}
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static void xilinx_free_msi_domains(struct xilinx_pcie *pcie)
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{
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struct irq_domain *parent = pcie->msi_domain->parent;
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irq_domain_remove(pcie->msi_domain);
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irq_domain_remove(parent);
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}
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/* INTx Functions */
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/**
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* xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
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* @domain: IRQ domain
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* @irq: Virtual IRQ number
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* @hwirq: HW interrupt number
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*
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* Return: Always returns 0.
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*/
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static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
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irq_hw_number_t hwirq)
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{
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irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
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irq_set_chip_data(irq, domain->host_data);
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return 0;
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}
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/* INTx IRQ Domain operations */
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static const struct irq_domain_ops intx_domain_ops = {
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.map = xilinx_pcie_intx_map,
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.xlate = pci_irqd_intx_xlate,
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};
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/* PCIe HW Functions */
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/**
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* xilinx_pcie_intr_handler - Interrupt Service Handler
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* @irq: IRQ number
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* @data: PCIe port information
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*
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* Return: IRQ_HANDLED on success and IRQ_NONE on failure
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||
|
|
*/
|
||
|
|
static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
|
||
|
|
{
|
||
|
|
struct xilinx_pcie *pcie = (struct xilinx_pcie *)data;
|
||
|
|
struct device *dev = pcie->dev;
|
||
|
|
u32 val, mask, status;
|
||
|
|
|
||
|
|
/* Read interrupt decode and mask registers */
|
||
|
|
val = pcie_read(pcie, XILINX_PCIE_REG_IDR);
|
||
|
|
mask = pcie_read(pcie, XILINX_PCIE_REG_IMR);
|
||
|
|
|
||
|
|
status = val & mask;
|
||
|
|
if (!status)
|
||
|
|
return IRQ_NONE;
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_LINK_DOWN)
|
||
|
|
dev_warn(dev, "Link Down\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_ECRC_ERR)
|
||
|
|
dev_warn(dev, "ECRC failed\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_STR_ERR)
|
||
|
|
dev_warn(dev, "Streaming error\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_HOT_RESET)
|
||
|
|
dev_info(dev, "Hot reset\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
|
||
|
|
dev_warn(dev, "ECAM access timeout\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_CORRECTABLE) {
|
||
|
|
dev_warn(dev, "Correctable error message\n");
|
||
|
|
xilinx_pcie_clear_err_interrupts(pcie);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_NONFATAL) {
|
||
|
|
dev_warn(dev, "Non fatal error message\n");
|
||
|
|
xilinx_pcie_clear_err_interrupts(pcie);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_FATAL) {
|
||
|
|
dev_warn(dev, "Fatal error message\n");
|
||
|
|
xilinx_pcie_clear_err_interrupts(pcie);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & (XILINX_PCIE_INTR_INTX | XILINX_PCIE_INTR_MSI)) {
|
||
|
|
struct irq_domain *domain;
|
||
|
|
|
||
|
|
val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR1);
|
||
|
|
|
||
|
|
/* Check whether interrupt valid */
|
||
|
|
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
|
||
|
|
dev_warn(dev, "RP Intr FIFO1 read error\n");
|
||
|
|
goto error;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Decode the IRQ number */
|
||
|
|
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
|
||
|
|
val = pcie_read(pcie, XILINX_PCIE_REG_RPIFR2) &
|
||
|
|
XILINX_PCIE_RPIFR2_MSG_DATA;
|
||
|
|
domain = pcie->msi_domain->parent;
|
||
|
|
} else {
|
||
|
|
val = (val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
|
||
|
|
XILINX_PCIE_RPIFR1_INTR_SHIFT;
|
||
|
|
domain = pcie->leg_domain;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Clear interrupt FIFO register 1 */
|
||
|
|
pcie_write(pcie, XILINX_PCIE_RPIFR1_ALL_MASK,
|
||
|
|
XILINX_PCIE_REG_RPIFR1);
|
||
|
|
|
||
|
|
generic_handle_domain_irq(domain, val);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
|
||
|
|
dev_warn(dev, "Slave unsupported request\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_UNEXP)
|
||
|
|
dev_warn(dev, "Slave unexpected completion\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_COMPL)
|
||
|
|
dev_warn(dev, "Slave completion timeout\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_ERRP)
|
||
|
|
dev_warn(dev, "Slave Error Poison\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_CMPABT)
|
||
|
|
dev_warn(dev, "Slave Completer Abort\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
|
||
|
|
dev_warn(dev, "Slave Illegal Burst\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_MST_DECERR)
|
||
|
|
dev_warn(dev, "Master decode error\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_MST_SLVERR)
|
||
|
|
dev_warn(dev, "Master slave error\n");
|
||
|
|
|
||
|
|
if (status & XILINX_PCIE_INTR_MST_ERRP)
|
||
|
|
dev_warn(dev, "Master error poison\n");
|
||
|
|
|
||
|
|
error:
|
||
|
|
/* Clear the Interrupt Decode register */
|
||
|
|
pcie_write(pcie, status, XILINX_PCIE_REG_IDR);
|
||
|
|
|
||
|
|
return IRQ_HANDLED;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* xilinx_pcie_init_irq_domain - Initialize IRQ domain
|
||
|
|
* @pcie: PCIe port information
|
||
|
|
*
|
||
|
|
* Return: '0' on success and error value on failure
|
||
|
|
*/
|
||
|
|
static int xilinx_pcie_init_irq_domain(struct xilinx_pcie *pcie)
|
||
|
|
{
|
||
|
|
struct device *dev = pcie->dev;
|
||
|
|
struct device_node *pcie_intc_node;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
/* Setup INTx */
|
||
|
|
pcie_intc_node = of_get_next_child(dev->of_node, NULL);
|
||
|
|
if (!pcie_intc_node) {
|
||
|
|
dev_err(dev, "No PCIe Intc node found\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
pcie->leg_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
|
||
|
|
&intx_domain_ops,
|
||
|
|
pcie);
|
||
|
|
of_node_put(pcie_intc_node);
|
||
|
|
if (!pcie->leg_domain) {
|
||
|
|
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||
|
|
return -ENODEV;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Setup MSI */
|
||
|
|
if (IS_ENABLED(CONFIG_PCI_MSI)) {
|
||
|
|
phys_addr_t pa = ALIGN_DOWN(virt_to_phys(pcie), SZ_4K);
|
||
|
|
|
||
|
|
ret = xilinx_allocate_msi_domains(pcie);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
pcie_write(pcie, upper_32_bits(pa), XILINX_PCIE_REG_MSIBASE1);
|
||
|
|
pcie_write(pcie, lower_32_bits(pa), XILINX_PCIE_REG_MSIBASE2);
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* xilinx_pcie_init_port - Initialize hardware
|
||
|
|
* @pcie: PCIe port information
|
||
|
|
*/
|
||
|
|
static void xilinx_pcie_init_port(struct xilinx_pcie *pcie)
|
||
|
|
{
|
||
|
|
struct device *dev = pcie->dev;
|
||
|
|
|
||
|
|
if (xilinx_pcie_link_up(pcie))
|
||
|
|
dev_info(dev, "PCIe Link is UP\n");
|
||
|
|
else
|
||
|
|
dev_info(dev, "PCIe Link is DOWN\n");
|
||
|
|
|
||
|
|
/* Disable all interrupts */
|
||
|
|
pcie_write(pcie, ~XILINX_PCIE_IDR_ALL_MASK,
|
||
|
|
XILINX_PCIE_REG_IMR);
|
||
|
|
|
||
|
|
/* Clear pending interrupts */
|
||
|
|
pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_IDR) &
|
||
|
|
XILINX_PCIE_IMR_ALL_MASK,
|
||
|
|
XILINX_PCIE_REG_IDR);
|
||
|
|
|
||
|
|
/* Enable all interrupts we handle */
|
||
|
|
pcie_write(pcie, XILINX_PCIE_IMR_ENABLE_MASK, XILINX_PCIE_REG_IMR);
|
||
|
|
|
||
|
|
/* Enable the Bridge enable bit */
|
||
|
|
pcie_write(pcie, pcie_read(pcie, XILINX_PCIE_REG_RPSC) |
|
||
|
|
XILINX_PCIE_REG_RPSC_BEN,
|
||
|
|
XILINX_PCIE_REG_RPSC);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* xilinx_pcie_parse_dt - Parse Device tree
|
||
|
|
* @pcie: PCIe port information
|
||
|
|
*
|
||
|
|
* Return: '0' on success and error value on failure
|
||
|
|
*/
|
||
|
|
static int xilinx_pcie_parse_dt(struct xilinx_pcie *pcie)
|
||
|
|
{
|
||
|
|
struct device *dev = pcie->dev;
|
||
|
|
struct device_node *node = dev->of_node;
|
||
|
|
struct resource regs;
|
||
|
|
unsigned int irq;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
err = of_address_to_resource(node, 0, ®s);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "missing \"reg\" property\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
pcie->reg_base = devm_pci_remap_cfg_resource(dev, ®s);
|
||
|
|
if (IS_ERR(pcie->reg_base))
|
||
|
|
return PTR_ERR(pcie->reg_base);
|
||
|
|
|
||
|
|
irq = irq_of_parse_and_map(node, 0);
|
||
|
|
err = devm_request_irq(dev, irq, xilinx_pcie_intr_handler,
|
||
|
|
IRQF_SHARED | IRQF_NO_THREAD,
|
||
|
|
"xilinx-pcie", pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "unable to request irq %d\n", irq);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* xilinx_pcie_probe - Probe function
|
||
|
|
* @pdev: Platform device pointer
|
||
|
|
*
|
||
|
|
* Return: '0' on success and error value on failure
|
||
|
|
*/
|
||
|
|
static int xilinx_pcie_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
struct xilinx_pcie *pcie;
|
||
|
|
struct pci_host_bridge *bridge;
|
||
|
|
int err;
|
||
|
|
|
||
|
|
if (!dev->of_node)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
|
||
|
|
if (!bridge)
|
||
|
|
return -ENODEV;
|
||
|
|
|
||
|
|
pcie = pci_host_bridge_priv(bridge);
|
||
|
|
mutex_init(&pcie->map_lock);
|
||
|
|
pcie->dev = dev;
|
||
|
|
|
||
|
|
err = xilinx_pcie_parse_dt(pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "Parsing DT failed\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
xilinx_pcie_init_port(pcie);
|
||
|
|
|
||
|
|
err = xilinx_pcie_init_irq_domain(pcie);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "Failed creating IRQ Domain\n");
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
bridge->sysdata = pcie;
|
||
|
|
bridge->ops = &xilinx_pcie_ops;
|
||
|
|
|
||
|
|
err = pci_host_probe(bridge);
|
||
|
|
if (err)
|
||
|
|
xilinx_free_msi_domains(pcie);
|
||
|
|
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct of_device_id xilinx_pcie_of_match[] = {
|
||
|
|
{ .compatible = "xlnx,axi-pcie-host-1.00.a", },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
static struct platform_driver xilinx_pcie_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "xilinx-pcie",
|
||
|
|
.of_match_table = xilinx_pcie_of_match,
|
||
|
|
.suppress_bind_attrs = true,
|
||
|
|
},
|
||
|
|
.probe = xilinx_pcie_probe,
|
||
|
|
};
|
||
|
|
builtin_platform_driver(xilinx_pcie_driver);
|