385 lines
11 KiB
C
385 lines
11 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2021 Marvell
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*
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* Authors:
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* Konstantin Porotchkin <kostap@marvell.com>
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*
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* Marvell CP110 UTMI PHY driver
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*/
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/phy/phy.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/usb/of.h>
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#include <linux/usb/otg.h>
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#define UTMI_PHY_PORTS 2
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/* CP110 UTMI register macro definetions */
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#define SYSCON_USB_CFG_REG 0x420
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#define USB_CFG_DEVICE_EN_MASK BIT(0)
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#define USB_CFG_DEVICE_MUX_OFFSET 1
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#define USB_CFG_DEVICE_MUX_MASK BIT(1)
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#define USB_CFG_PLL_MASK BIT(25)
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#define SYSCON_UTMI_CFG_REG(id) (0x440 + (id) * 4)
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#define UTMI_PHY_CFG_PU_MASK BIT(5)
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#define UTMI_PLL_CTRL_REG 0x0
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#define PLL_REFDIV_OFFSET 0
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#define PLL_REFDIV_MASK GENMASK(6, 0)
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#define PLL_REFDIV_VAL 0x5
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#define PLL_FBDIV_OFFSET 16
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#define PLL_FBDIV_MASK GENMASK(24, 16)
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#define PLL_FBDIV_VAL 0x60
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#define PLL_SEL_LPFR_MASK GENMASK(29, 28)
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#define PLL_RDY BIT(31)
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#define UTMI_CAL_CTRL_REG 0x8
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#define IMPCAL_VTH_OFFSET 8
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#define IMPCAL_VTH_MASK GENMASK(10, 8)
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#define IMPCAL_VTH_VAL 0x7
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#define IMPCAL_DONE BIT(23)
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#define PLLCAL_DONE BIT(31)
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#define UTMI_TX_CH_CTRL_REG 0xC
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#define DRV_EN_LS_OFFSET 12
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#define DRV_EN_LS_MASK GENMASK(15, 12)
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#define IMP_SEL_LS_OFFSET 16
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#define IMP_SEL_LS_MASK GENMASK(19, 16)
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#define TX_AMP_OFFSET 20
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#define TX_AMP_MASK GENMASK(22, 20)
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#define TX_AMP_VAL 0x4
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#define UTMI_RX_CH_CTRL0_REG 0x14
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#define SQ_DET_EN BIT(15)
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#define SQ_ANA_DTC_SEL BIT(28)
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#define UTMI_RX_CH_CTRL1_REG 0x18
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#define SQ_AMP_CAL_OFFSET 0
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#define SQ_AMP_CAL_MASK GENMASK(2, 0)
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#define SQ_AMP_CAL_VAL 1
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#define SQ_AMP_CAL_EN BIT(3)
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#define UTMI_CTRL_STATUS0_REG 0x24
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#define SUSPENDM BIT(22)
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#define TEST_SEL BIT(25)
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#define UTMI_CHGDTC_CTRL_REG 0x38
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#define VDAT_OFFSET 8
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#define VDAT_MASK GENMASK(9, 8)
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#define VDAT_VAL 1
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#define VSRC_OFFSET 10
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#define VSRC_MASK GENMASK(11, 10)
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#define VSRC_VAL 1
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#define PLL_LOCK_DELAY_US 10000
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#define PLL_LOCK_TIMEOUT_US 1000000
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#define PORT_REGS(p) ((p)->priv->regs + (p)->id * 0x1000)
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/**
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* struct mvebu_cp110_utmi - PHY driver data
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*
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* @regs: PHY registers
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* @syscon: Regmap with system controller registers
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* @dev: device driver handle
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* @ops: phy ops
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*/
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struct mvebu_cp110_utmi {
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void __iomem *regs;
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struct regmap *syscon;
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struct device *dev;
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const struct phy_ops *ops;
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};
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/**
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* struct mvebu_cp110_utmi_port - PHY port data
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*
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* @priv: PHY driver data
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* @id: PHY port ID
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* @dr_mode: PHY connection: USB_DR_MODE_HOST or USB_DR_MODE_PERIPHERAL
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*/
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struct mvebu_cp110_utmi_port {
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struct mvebu_cp110_utmi *priv;
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u32 id;
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enum usb_dr_mode dr_mode;
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};
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static void mvebu_cp110_utmi_port_setup(struct mvebu_cp110_utmi_port *port)
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{
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u32 reg;
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/*
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* Setup PLL.
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* The reference clock is the frequency of quartz resonator
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* connected to pins REFCLK_XIN and REFCLK_XOUT of the SoC.
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* Register init values are matching the 40MHz default clock.
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* The crystal used for all platform boards is now 25MHz.
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* See the functional specification for details.
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*/
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reg = readl(PORT_REGS(port) + UTMI_PLL_CTRL_REG);
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reg &= ~(PLL_REFDIV_MASK | PLL_FBDIV_MASK | PLL_SEL_LPFR_MASK);
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reg |= (PLL_REFDIV_VAL << PLL_REFDIV_OFFSET) |
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(PLL_FBDIV_VAL << PLL_FBDIV_OFFSET);
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writel(reg, PORT_REGS(port) + UTMI_PLL_CTRL_REG);
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/* Impedance Calibration Threshold Setting */
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reg = readl(PORT_REGS(port) + UTMI_CAL_CTRL_REG);
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reg &= ~IMPCAL_VTH_MASK;
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reg |= IMPCAL_VTH_VAL << IMPCAL_VTH_OFFSET;
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writel(reg, PORT_REGS(port) + UTMI_CAL_CTRL_REG);
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/* Set LS TX driver strength coarse control */
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reg = readl(PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
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reg &= ~TX_AMP_MASK;
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reg |= TX_AMP_VAL << TX_AMP_OFFSET;
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writel(reg, PORT_REGS(port) + UTMI_TX_CH_CTRL_REG);
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/* Disable SQ and enable analog squelch detect */
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reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
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reg &= ~SQ_DET_EN;
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reg |= SQ_ANA_DTC_SEL;
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writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL0_REG);
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/*
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* Set External squelch calibration number and
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* enable the External squelch calibration
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*/
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reg = readl(PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
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reg &= ~SQ_AMP_CAL_MASK;
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reg |= (SQ_AMP_CAL_VAL << SQ_AMP_CAL_OFFSET) | SQ_AMP_CAL_EN;
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writel(reg, PORT_REGS(port) + UTMI_RX_CH_CTRL1_REG);
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/*
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* Set Control VDAT Reference Voltage - 0.325V and
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* Control VSRC Reference Voltage - 0.6V
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*/
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reg = readl(PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
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reg &= ~(VDAT_MASK | VSRC_MASK);
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reg |= (VDAT_VAL << VDAT_OFFSET) | (VSRC_VAL << VSRC_OFFSET);
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writel(reg, PORT_REGS(port) + UTMI_CHGDTC_CTRL_REG);
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}
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static int mvebu_cp110_utmi_phy_power_off(struct phy *phy)
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{
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struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
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struct mvebu_cp110_utmi *utmi = port->priv;
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int i;
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/* Power down UTMI PHY port */
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regmap_clear_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
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UTMI_PHY_CFG_PU_MASK);
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for (i = 0; i < UTMI_PHY_PORTS; i++) {
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int test = regmap_test_bits(utmi->syscon,
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SYSCON_UTMI_CFG_REG(i),
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UTMI_PHY_CFG_PU_MASK);
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/* skip PLL shutdown if there are active UTMI PHY ports */
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if (test != 0)
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return 0;
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}
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/* PLL Power down if all UTMI PHYs are down */
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regmap_clear_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
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return 0;
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}
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static int mvebu_cp110_utmi_phy_power_on(struct phy *phy)
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{
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struct mvebu_cp110_utmi_port *port = phy_get_drvdata(phy);
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struct mvebu_cp110_utmi *utmi = port->priv;
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struct device *dev = &phy->dev;
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int ret;
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u32 reg;
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/* It is necessary to power off UTMI before configuration */
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ret = mvebu_cp110_utmi_phy_power_off(phy);
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if (ret) {
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dev_err(dev, "UTMI power OFF before power ON failed\n");
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return ret;
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}
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/*
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* If UTMI port is connected to USB Device controller,
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* configure the USB MUX prior to UTMI PHY initialization.
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* The single USB device controller can be connected
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* to UTMI0 or to UTMI1 PHY port, but not to both.
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*/
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if (port->dr_mode == USB_DR_MODE_PERIPHERAL) {
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regmap_update_bits(utmi->syscon, SYSCON_USB_CFG_REG,
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USB_CFG_DEVICE_EN_MASK | USB_CFG_DEVICE_MUX_MASK,
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USB_CFG_DEVICE_EN_MASK |
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(port->id << USB_CFG_DEVICE_MUX_OFFSET));
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}
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/* Set Test suspendm mode and enable Test UTMI select */
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reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
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reg |= SUSPENDM | TEST_SEL;
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writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
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/* Wait for UTMI power down */
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mdelay(1);
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/* PHY port setup first */
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mvebu_cp110_utmi_port_setup(port);
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/* Power UP UTMI PHY */
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regmap_set_bits(utmi->syscon, SYSCON_UTMI_CFG_REG(port->id),
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UTMI_PHY_CFG_PU_MASK);
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/* Disable Test UTMI select */
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reg = readl(PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
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reg &= ~TEST_SEL;
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writel(reg, PORT_REGS(port) + UTMI_CTRL_STATUS0_REG);
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/* Wait for impedance calibration */
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ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
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reg & IMPCAL_DONE,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "Failed to end UTMI impedance calibration\n");
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return ret;
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}
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/* Wait for PLL calibration */
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ret = readl_poll_timeout(PORT_REGS(port) + UTMI_CAL_CTRL_REG, reg,
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reg & PLLCAL_DONE,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "Failed to end UTMI PLL calibration\n");
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return ret;
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}
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/* Wait for PLL ready */
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ret = readl_poll_timeout(PORT_REGS(port) + UTMI_PLL_CTRL_REG, reg,
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reg & PLL_RDY,
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PLL_LOCK_DELAY_US, PLL_LOCK_TIMEOUT_US);
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if (ret) {
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dev_err(dev, "PLL is not ready\n");
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return ret;
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}
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/* PLL Power up */
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regmap_set_bits(utmi->syscon, SYSCON_USB_CFG_REG, USB_CFG_PLL_MASK);
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return 0;
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}
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static const struct phy_ops mvebu_cp110_utmi_phy_ops = {
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.power_on = mvebu_cp110_utmi_phy_power_on,
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.power_off = mvebu_cp110_utmi_phy_power_off,
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.owner = THIS_MODULE,
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};
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static const struct of_device_id mvebu_cp110_utmi_of_match[] = {
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{ .compatible = "marvell,cp110-utmi-phy" },
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{},
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};
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MODULE_DEVICE_TABLE(of, mvebu_cp110_utmi_of_match);
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static int mvebu_cp110_utmi_phy_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct mvebu_cp110_utmi *utmi;
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struct phy_provider *provider;
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struct device_node *child;
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u32 usb_devices = 0;
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utmi = devm_kzalloc(dev, sizeof(*utmi), GFP_KERNEL);
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if (!utmi)
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return -ENOMEM;
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utmi->dev = dev;
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/* Get system controller region */
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utmi->syscon = syscon_regmap_lookup_by_phandle(dev->of_node,
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"marvell,system-controller");
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if (IS_ERR(utmi->syscon)) {
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dev_err(dev, "Missing UTMI system controller\n");
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return PTR_ERR(utmi->syscon);
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}
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/* Get UTMI memory region */
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utmi->regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(utmi->regs))
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return PTR_ERR(utmi->regs);
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for_each_available_child_of_node(dev->of_node, child) {
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struct mvebu_cp110_utmi_port *port;
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struct phy *phy;
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int ret;
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u32 port_id;
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ret = of_property_read_u32(child, "reg", &port_id);
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if ((ret < 0) || (port_id >= UTMI_PHY_PORTS)) {
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dev_err(dev,
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"invalid 'reg' property on child %pOF\n",
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child);
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continue;
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}
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port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
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if (!port) {
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of_node_put(child);
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return -ENOMEM;
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}
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port->dr_mode = of_usb_get_dr_mode_by_phy(child, -1);
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if ((port->dr_mode != USB_DR_MODE_HOST) &&
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(port->dr_mode != USB_DR_MODE_PERIPHERAL)) {
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dev_err(&pdev->dev,
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"Missing dual role setting of the port%d, will use HOST mode\n",
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port_id);
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port->dr_mode = USB_DR_MODE_HOST;
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}
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if (port->dr_mode == USB_DR_MODE_PERIPHERAL) {
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usb_devices++;
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if (usb_devices > 1) {
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dev_err(dev,
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"Single USB device allowed! Port%d will use HOST mode\n",
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||
|
|
port_id);
|
||
|
|
port->dr_mode = USB_DR_MODE_HOST;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Retrieve PHY capabilities */
|
||
|
|
utmi->ops = &mvebu_cp110_utmi_phy_ops;
|
||
|
|
|
||
|
|
/* Instantiate the PHY */
|
||
|
|
phy = devm_phy_create(dev, child, utmi->ops);
|
||
|
|
if (IS_ERR(phy)) {
|
||
|
|
dev_err(dev, "Failed to create the UTMI PHY\n");
|
||
|
|
of_node_put(child);
|
||
|
|
return PTR_ERR(phy);
|
||
|
|
}
|
||
|
|
|
||
|
|
port->priv = utmi;
|
||
|
|
port->id = port_id;
|
||
|
|
phy_set_drvdata(phy, port);
|
||
|
|
|
||
|
|
/* Ensure the PHY is powered off */
|
||
|
|
mvebu_cp110_utmi_phy_power_off(phy);
|
||
|
|
}
|
||
|
|
|
||
|
|
dev_set_drvdata(dev, utmi);
|
||
|
|
provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
|
||
|
|
|
||
|
|
return PTR_ERR_OR_ZERO(provider);
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct platform_driver mvebu_cp110_utmi_driver = {
|
||
|
|
.probe = mvebu_cp110_utmi_phy_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "mvebu-cp110-utmi-phy",
|
||
|
|
.of_match_table = mvebu_cp110_utmi_of_match,
|
||
|
|
},
|
||
|
|
};
|
||
|
|
module_platform_driver(mvebu_cp110_utmi_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Konstatin Porotchkin <kostap@marvell.com>");
|
||
|
|
MODULE_DESCRIPTION("Marvell Armada CP110 UTMI PHY driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|