251 lines
8.0 KiB
C
251 lines
8.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Core pinctrl/GPIO driver for Intel GPIO controllers
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*
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* Copyright (C) 2015, Intel Corporation
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* Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
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* Mika Westerberg <mika.westerberg@linux.intel.com>
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*/
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#ifndef PINCTRL_INTEL_H
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#define PINCTRL_INTEL_H
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#include <linux/bits.h>
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#include <linux/compiler_types.h>
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#include <linux/gpio/driver.h>
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#include <linux/irq.h>
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#include <linux/kernel.h>
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#include <linux/pm.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/spinlock_types.h>
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struct platform_device;
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struct device;
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/**
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* struct intel_pingroup - Description about group of pins
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* @grp: Generic data of the pin group (name and pins)
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* @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
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* @modes: If not %NULL this will hold mode for each pin in @pins
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*/
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struct intel_pingroup {
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struct pingroup grp;
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unsigned short mode;
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const unsigned int *modes;
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};
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/**
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* struct intel_function - Description about a function
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* @name: Name of the function
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* @groups: An array of groups for this function
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* @ngroups: Number of groups in @groups
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*/
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struct intel_function {
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const char *name;
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const char * const *groups;
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size_t ngroups;
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};
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/**
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* struct intel_padgroup - Hardware pad group information
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* @reg_num: GPI_IS register number
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* @base: Starting pin of this group
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* @size: Size of this group (maximum is 32).
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* @gpio_base: Starting GPIO base of this group
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* @padown_num: PAD_OWN register number (assigned by the core driver)
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*
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* If pad groups of a community are not the same size, use this structure
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* to specify them.
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*/
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struct intel_padgroup {
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unsigned int reg_num;
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unsigned int base;
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unsigned int size;
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int gpio_base;
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unsigned int padown_num;
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};
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/**
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* enum - Special treatment for GPIO base in pad group
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*
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* @INTEL_GPIO_BASE_ZERO: force GPIO base to be 0
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* @INTEL_GPIO_BASE_NOMAP: no GPIO mapping should be created
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* @INTEL_GPIO_BASE_MATCH: matches with starting pin number
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*/
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enum {
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INTEL_GPIO_BASE_ZERO = -2,
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INTEL_GPIO_BASE_NOMAP = -1,
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INTEL_GPIO_BASE_MATCH = 0,
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};
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/**
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* struct intel_community - Intel pin community description
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* @barno: MMIO BAR number where registers for this community reside
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* @padown_offset: Register offset of PAD_OWN register from @regs. If %0
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* then there is no support for owner.
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* @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
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* locking is not supported.
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* @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
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* is assumed that the host owns the pin (rather than
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* ACPI).
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* @is_offset: Register offset of GPI_IS from @regs.
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* @ie_offset: Register offset of GPI_IE from @regs.
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* @features: Additional features supported by the hardware
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* @pin_base: Starting pin of pins in this community
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* @npins: Number of pins in this community
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* @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
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* HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
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* @gpp_num_padown_regs: Number of pad registers each pad group consumes at
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* minimum. Use %0 if the number of registers can be
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* determined by the size of the group.
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* @gpps: Pad groups if the controller has variable size pad groups
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* @ngpps: Number of pad groups in this community
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* @pad_map: Optional non-linear mapping of the pads
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* @nirqs: Optional total number of IRQs this community can generate
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* @acpi_space_id: Optional address space ID for ACPI OpRegion handler
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* @regs: Community specific common registers (reserved for core driver)
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* @pad_regs: Community specific pad registers (reserved for core driver)
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*
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* In some of Intel GPIO host controllers this driver supports each pad group
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* is of equal size (except the last one). In that case the driver can just
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* fill in @gpp_size field and let the core driver to handle the rest. If
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* the controller has pad groups of variable size the client driver can
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* pass custom @gpps and @ngpps instead.
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*/
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struct intel_community {
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unsigned int barno;
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unsigned int padown_offset;
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unsigned int padcfglock_offset;
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unsigned int hostown_offset;
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unsigned int is_offset;
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unsigned int ie_offset;
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unsigned int features;
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unsigned int pin_base;
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size_t npins;
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unsigned int gpp_size;
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unsigned int gpp_num_padown_regs;
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const struct intel_padgroup *gpps;
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size_t ngpps;
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const unsigned int *pad_map;
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unsigned short nirqs;
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unsigned short acpi_space_id;
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/* Reserved for the core driver */
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void __iomem *regs;
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void __iomem *pad_regs;
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};
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/* Additional features supported by the hardware */
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#define PINCTRL_FEATURE_DEBOUNCE BIT(0)
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#define PINCTRL_FEATURE_1K_PD BIT(1)
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#define PINCTRL_FEATURE_GPIO_HW_INFO BIT(2)
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#define PINCTRL_FEATURE_PWM BIT(3)
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#define PINCTRL_FEATURE_BLINK BIT(4)
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#define PINCTRL_FEATURE_EXP BIT(5)
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/**
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* PIN_GROUP - Declare a pin group
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* @n: Name of the group
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* @p: An array of pins this group consists
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* @m: Mode which the pins are put when this group is active. Can be either
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* a single integer or an array of integers in which case mode is per
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* pin.
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*/
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#define PIN_GROUP(n, p, m) \
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{ \
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.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))), \
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.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0), \
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.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)), \
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}
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#define FUNCTION(n, g) \
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{ \
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.name = (n), \
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.groups = (g), \
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.ngroups = ARRAY_SIZE((g)), \
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}
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/**
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* struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
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* @uid: ACPI _UID for the probe driver use if needed
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* @pins: Array if pins this pinctrl controls
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* @npins: Number of pins in the array
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* @groups: Array of pin groups
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* @ngroups: Number of groups in the array
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* @functions: Array of functions
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* @nfunctions: Number of functions in the array
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* @communities: Array of communities this pinctrl handles
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* @ncommunities: Number of communities in the array
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*
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* The @communities is used as a template by the core driver. It will make
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* copy of all communities and fill in rest of the information.
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*/
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struct intel_pinctrl_soc_data {
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const char *uid;
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const struct pinctrl_pin_desc *pins;
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size_t npins;
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const struct intel_pingroup *groups;
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size_t ngroups;
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const struct intel_function *functions;
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size_t nfunctions;
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const struct intel_community *communities;
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size_t ncommunities;
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};
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const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
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struct intel_pad_context;
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struct intel_community_context;
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/**
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* struct intel_pinctrl_context - context to be saved during suspend-resume
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* @pads: Opaque context per pad (driver dependent)
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* @communities: Opaque context per community (driver dependent)
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*/
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struct intel_pinctrl_context {
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struct intel_pad_context *pads;
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struct intel_community_context *communities;
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};
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/**
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* struct intel_pinctrl - Intel pinctrl private structure
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* @dev: Pointer to the device structure
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* @lock: Lock to serialize register access
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* @pctldesc: Pin controller description
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* @pctldev: Pointer to the pin controller device
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* @chip: GPIO chip in this pin controller
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* @soc: SoC/PCH specific pin configuration data
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* @communities: All communities in this pin controller
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* @ncommunities: Number of communities in this pin controller
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* @context: Configuration saved over system sleep
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* @irq: pinctrl/GPIO chip irq number
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*/
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struct intel_pinctrl {
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struct device *dev;
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raw_spinlock_t lock;
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struct pinctrl_desc pctldesc;
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struct pinctrl_dev *pctldev;
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struct gpio_chip chip;
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const struct intel_pinctrl_soc_data *soc;
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struct intel_community *communities;
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size_t ncommunities;
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struct intel_pinctrl_context context;
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int irq;
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};
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int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
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int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
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#ifdef CONFIG_PM_SLEEP
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int intel_pinctrl_suspend_noirq(struct device *dev);
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int intel_pinctrl_resume_noirq(struct device *dev);
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#endif
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#define INTEL_PINCTRL_PM_OPS(_name) \
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const struct dev_pm_ops _name = { \
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SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(intel_pinctrl_suspend_noirq, \
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intel_pinctrl_resume_noirq) \
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}
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#endif /* PINCTRL_INTEL_H */
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