86 lines
1.8 KiB
C
86 lines
1.8 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Device Tree binding constants for Actions Semi S500 Clock Management Unit
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*
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* Copyright (c) 2014 Actions Semi Inc.
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* Copyright (c) 2018 LSI-TEC - Caninos Loucos
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*/
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#ifndef __DT_BINDINGS_CLOCK_S500_CMU_H
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#define __DT_BINDINGS_CLOCK_S500_CMU_H
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#define CLK_NONE 0
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/* fixed rate clocks */
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#define CLK_LOSC 1
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#define CLK_HOSC 2
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/* pll clocks */
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#define CLK_CORE_PLL 3
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#define CLK_DEV_PLL 4
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#define CLK_DDR_PLL 5
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#define CLK_NAND_PLL 6
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#define CLK_DISPLAY_PLL 7
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#define CLK_ETHERNET_PLL 8
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#define CLK_AUDIO_PLL 9
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/* system clock */
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#define CLK_DEV 10
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#define CLK_H 11
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#define CLK_AHBPREDIV 12
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#define CLK_AHB 13
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#define CLK_DE 14
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#define CLK_BISP 15
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#define CLK_VCE 16
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#define CLK_VDE 17
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/* peripheral device clock */
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#define CLK_TIMER 18
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#define CLK_I2C0 19
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#define CLK_I2C1 20
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#define CLK_I2C2 21
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#define CLK_I2C3 22
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#define CLK_PWM0 23
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#define CLK_PWM1 24
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#define CLK_PWM2 25
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#define CLK_PWM3 26
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#define CLK_PWM4 27
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#define CLK_PWM5 28
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#define CLK_SD0 29
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#define CLK_SD1 30
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#define CLK_SD2 31
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#define CLK_SENSOR0 32
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#define CLK_SENSOR1 33
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#define CLK_SPI0 34
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#define CLK_SPI1 35
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#define CLK_SPI2 36
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#define CLK_SPI3 37
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#define CLK_UART0 38
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#define CLK_UART1 39
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#define CLK_UART2 40
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#define CLK_UART3 41
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#define CLK_UART4 42
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#define CLK_UART5 43
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#define CLK_UART6 44
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#define CLK_DE1 45
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#define CLK_DE2 46
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#define CLK_I2SRX 47
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#define CLK_I2STX 48
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#define CLK_HDMI_AUDIO 49
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#define CLK_HDMI 50
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#define CLK_SPDIF 51
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#define CLK_NAND 52
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#define CLK_ECC 53
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#define CLK_RMII_REF 54
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#define CLK_GPIO 55
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/* additional clocks */
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#define CLK_APB 56
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#define CLK_DMAC 57
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#define CLK_NIC 58
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#define CLK_ETHERNET 59
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#define CLK_NR_CLKS (CLK_ETHERNET + 1)
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#endif /* __DT_BINDINGS_CLOCK_S500_CMU_H */
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