132 lines
5.3 KiB
C
132 lines
5.3 KiB
C
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2017 Texas Instruments, Inc.
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*/
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#ifndef __DT_BINDINGS_CLK_OMAP5_H
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#define __DT_BINDINGS_CLK_OMAP5_H
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#define OMAP5_CLKCTRL_OFFSET 0x20
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#define OMAP5_CLKCTRL_INDEX(offset) ((offset) - OMAP5_CLKCTRL_OFFSET)
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/* mpu clocks */
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#define OMAP5_MPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* dsp clocks */
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#define OMAP5_MMU_DSP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* abe clocks */
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#define OMAP5_L4_ABE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_AESS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MCPDM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_DMIC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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#define OMAP5_MCBSP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
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#define OMAP5_MCBSP2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
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#define OMAP5_MCBSP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
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#define OMAP5_TIMER5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
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#define OMAP5_TIMER6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
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#define OMAP5_TIMER7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
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#define OMAP5_TIMER8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
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/* l3main1 clocks */
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#define OMAP5_L3_MAIN_1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* l3main2 clocks */
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#define OMAP5_L3_MAIN_2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_L3_MAIN_2_GPMC_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_L3_MAIN_2_OCMC_RAM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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/* ipu clocks */
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#define OMAP5_MMU_IPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* dma clocks */
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#define OMAP5_DMA_SYSTEM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* emif clocks */
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#define OMAP5_DMM_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_EMIF1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_EMIF2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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/* l4cfg clocks */
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#define OMAP5_L4_CFG_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_SPINLOCK_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MAILBOX_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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/* l3instr clocks */
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#define OMAP5_L3_MAIN_3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_L3_INSTR_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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/* l4per clocks */
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#define OMAP5_TIMER10_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_TIMER11_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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#define OMAP5_TIMER3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
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#define OMAP5_TIMER4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x48)
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#define OMAP5_TIMER9_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
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#define OMAP5_GPIO2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x60)
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#define OMAP5_GPIO3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
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#define OMAP5_GPIO4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x70)
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#define OMAP5_GPIO5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
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#define OMAP5_GPIO6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x80)
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#define OMAP5_I2C1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa0)
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#define OMAP5_I2C2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xa8)
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#define OMAP5_I2C3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb0)
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#define OMAP5_I2C4_CLKCTRL OMAP5_CLKCTRL_INDEX(0xb8)
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#define OMAP5_L4_PER_CLKCTRL OMAP5_CLKCTRL_INDEX(0xc0)
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#define OMAP5_MCSPI1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
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#define OMAP5_MCSPI2_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf8)
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#define OMAP5_MCSPI3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x100)
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#define OMAP5_MCSPI4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x108)
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#define OMAP5_GPIO7_CLKCTRL OMAP5_CLKCTRL_INDEX(0x110)
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#define OMAP5_GPIO8_CLKCTRL OMAP5_CLKCTRL_INDEX(0x118)
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#define OMAP5_MMC3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x120)
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#define OMAP5_MMC4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x128)
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#define OMAP5_UART1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x140)
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#define OMAP5_UART2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x148)
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#define OMAP5_UART3_CLKCTRL OMAP5_CLKCTRL_INDEX(0x150)
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#define OMAP5_UART4_CLKCTRL OMAP5_CLKCTRL_INDEX(0x158)
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#define OMAP5_MMC5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x160)
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#define OMAP5_I2C5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x168)
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#define OMAP5_UART5_CLKCTRL OMAP5_CLKCTRL_INDEX(0x170)
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#define OMAP5_UART6_CLKCTRL OMAP5_CLKCTRL_INDEX(0x178)
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/* l4_secure clocks */
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#define OMAP5_L4_SECURE_CLKCTRL_OFFSET 0x1a0
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#define OMAP5_L4_SECURE_CLKCTRL_INDEX(offset) ((offset) - OMAP5_L4_SECURE_CLKCTRL_OFFSET)
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#define OMAP5_AES1_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a0)
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#define OMAP5_AES2_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1a8)
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#define OMAP5_DES3DES_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b0)
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#define OMAP5_FPKA_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1b8)
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#define OMAP5_RNG_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c0)
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#define OMAP5_SHA2MD5_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1c8)
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#define OMAP5_DMA_CRYPTO_CLKCTRL OMAP5_L4_SECURE_CLKCTRL_INDEX(0x1d8)
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/* iva clocks */
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#define OMAP5_IVA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_SL2IF_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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/* dss clocks */
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#define OMAP5_DSS_CORE_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* gpu clocks */
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#define OMAP5_GPU_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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/* l3init clocks */
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#define OMAP5_MMC1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x28)
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#define OMAP5_MMC2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_USB_HOST_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x58)
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#define OMAP5_USB_TLL_HS_CLKCTRL OMAP5_CLKCTRL_INDEX(0x68)
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#define OMAP5_SATA_CLKCTRL OMAP5_CLKCTRL_INDEX(0x88)
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#define OMAP5_OCP2SCP1_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe0)
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#define OMAP5_OCP2SCP3_CLKCTRL OMAP5_CLKCTRL_INDEX(0xe8)
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#define OMAP5_USB_OTG_SS_CLKCTRL OMAP5_CLKCTRL_INDEX(0xf0)
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/* wkupaon clocks */
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#define OMAP5_L4_WKUP_CLKCTRL OMAP5_CLKCTRL_INDEX(0x20)
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#define OMAP5_WD_TIMER2_CLKCTRL OMAP5_CLKCTRL_INDEX(0x30)
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#define OMAP5_GPIO1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x38)
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#define OMAP5_TIMER1_CLKCTRL OMAP5_CLKCTRL_INDEX(0x40)
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#define OMAP5_COUNTER_32K_CLKCTRL OMAP5_CLKCTRL_INDEX(0x50)
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#define OMAP5_KBD_CLKCTRL OMAP5_CLKCTRL_INDEX(0x78)
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#endif
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