60 lines
1.7 KiB
C
60 lines
1.7 KiB
C
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/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
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#define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R8A774E1 CPG Core Clocks */
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#define R8A774E1_CLK_Z 0
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#define R8A774E1_CLK_Z2 1
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#define R8A774E1_CLK_ZG 2
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#define R8A774E1_CLK_ZTR 3
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#define R8A774E1_CLK_ZTRD2 4
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#define R8A774E1_CLK_ZT 5
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#define R8A774E1_CLK_ZX 6
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#define R8A774E1_CLK_S0D1 7
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#define R8A774E1_CLK_S0D2 8
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#define R8A774E1_CLK_S0D3 9
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#define R8A774E1_CLK_S0D4 10
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#define R8A774E1_CLK_S0D6 11
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#define R8A774E1_CLK_S0D8 12
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#define R8A774E1_CLK_S0D12 13
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#define R8A774E1_CLK_S1D2 14
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#define R8A774E1_CLK_S1D4 15
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#define R8A774E1_CLK_S2D1 16
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#define R8A774E1_CLK_S2D2 17
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#define R8A774E1_CLK_S2D4 18
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#define R8A774E1_CLK_S3D1 19
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#define R8A774E1_CLK_S3D2 20
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#define R8A774E1_CLK_S3D4 21
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#define R8A774E1_CLK_LB 22
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#define R8A774E1_CLK_CL 23
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#define R8A774E1_CLK_ZB3 24
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#define R8A774E1_CLK_ZB3D2 25
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#define R8A774E1_CLK_ZB3D4 26
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#define R8A774E1_CLK_CR 27
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#define R8A774E1_CLK_CRD2 28
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#define R8A774E1_CLK_SD0H 29
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#define R8A774E1_CLK_SD0 30
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#define R8A774E1_CLK_SD1H 31
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#define R8A774E1_CLK_SD1 32
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#define R8A774E1_CLK_SD2H 33
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#define R8A774E1_CLK_SD2 34
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#define R8A774E1_CLK_SD3H 35
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#define R8A774E1_CLK_SD3 36
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#define R8A774E1_CLK_RPC 37
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#define R8A774E1_CLK_RPCD2 38
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#define R8A774E1_CLK_MSO 39
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#define R8A774E1_CLK_HDMI 40
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#define R8A774E1_CLK_CSI0 41
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#define R8A774E1_CLK_CP 42
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#define R8A774E1_CLK_CPEX 43
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#define R8A774E1_CLK_R 44
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#define R8A774E1_CLK_OSC 45
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#define R8A774E1_CLK_CANFD 46
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#endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */
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