422 lines
16 KiB
C
422 lines
16 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (C) 2022 MediaTek Inc.
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* Author: Yongqiang Niu <yongqiang.niu@mediatek.com>
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*/
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#ifndef _DT_BINDINGS_GCE_MT8186_H
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#define _DT_BINDINGS_GCE_MT8186_H
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/* assign timeout 0 also means default */
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#define CMDQ_NO_TIMEOUT 0xffffffff
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#define CMDQ_TIMEOUT_DEFAULT 1000
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/* GCE thread priority */
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#define CMDQ_THR_PRIO_LOWEST 0
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#define CMDQ_THR_PRIO_1 1
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#define CMDQ_THR_PRIO_2 2
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#define CMDQ_THR_PRIO_3 3
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#define CMDQ_THR_PRIO_4 4
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#define CMDQ_THR_PRIO_5 5
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#define CMDQ_THR_PRIO_6 6
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#define CMDQ_THR_PRIO_HIGHEST 7
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/* CPR count in 32bit register */
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#define GCE_CPR_COUNT 1312
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/* GCE subsys table */
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#define SUBSYS_1300XXXX 0
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#define SUBSYS_1400XXXX 1
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#define SUBSYS_1401XXXX 2
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#define SUBSYS_1402XXXX 3
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#define SUBSYS_1502XXXX 4
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#define SUBSYS_1582XXXX 5
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#define SUBSYS_1B00XXXX 6
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#define SUBSYS_1C00XXXX 7
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#define SUBSYS_1C10XXXX 8
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#define SUBSYS_1000XXXX 9
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#define SUBSYS_1001XXXX 10
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#define SUBSYS_1020XXXX 11
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#define SUBSYS_1021XXXX 12
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#define SUBSYS_1022XXXX 13
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#define SUBSYS_1023XXXX 14
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#define SUBSYS_1060XXXX 15
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#define SUBSYS_1602XXXX 16
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#define SUBSYS_1608XXXX 17
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#define SUBSYS_1700XXXX 18
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#define SUBSYS_1701XXXX 19
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#define SUBSYS_1702XXXX 20
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#define SUBSYS_1703XXXX 21
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#define SUBSYS_1706XXXX 22
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#define SUBSYS_1A00XXXX 23
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#define SUBSYS_1A01XXXX 24
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#define SUBSYS_1A02XXXX 25
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#define SUBSYS_1A03XXXX 26
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#define SUBSYS_1A04XXXX 27
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#define SUBSYS_1A05XXXX 28
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#define SUBSYS_1A06XXXX 29
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#define SUBSYS_NO_SUPPORT 99
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/* GCE General Purpose Register (GPR) support
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* Leave note for scenario usage here
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*/
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/* GCE: write mask */
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#define GCE_GPR_R00 0x00
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#define GCE_GPR_R01 0x01
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/* MDP: P1: JPEG dest */
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#define GCE_GPR_R02 0x02
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#define GCE_GPR_R03 0x03
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/* MDP: PQ color */
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#define GCE_GPR_R04 0x04
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/* MDP: 2D sharpness */
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#define GCE_GPR_R05 0x05
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/* DISP: poll esd */
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#define GCE_GPR_R06 0x06
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#define GCE_GPR_R07 0x07
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/* MDP: P4: 2D sharpness dst */
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#define GCE_GPR_R08 0x08
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#define GCE_GPR_R09 0x09
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/* VCU: poll with timeout for GPR timer */
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#define GCE_GPR_R10 0x0A
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#define GCE_GPR_R11 0x0B
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/* CMDQ: debug */
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#define GCE_GPR_R12 0x0C
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#define GCE_GPR_R13 0x0D
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/* CMDQ: P7: debug */
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#define GCE_GPR_R14 0x0E
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#define GCE_GPR_R15 0x0F
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/* GCE hardware events */
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/* VDEC */
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#define CMDQ_EVENT_LINE_COUNT_THRESHOLD_INTERRUPT 0
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#define CMDQ_EVENT_VDEC_INT 1
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#define CMDQ_EVENT_VDEC_PAUSE 2
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#define CMDQ_EVENT_VDEC_DEC_ERROR 3
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#define CMDQ_EVENT_MDEC_TIMEOUT 4
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#define CMDQ_EVENT_DRAM_ACCESS_DONE 5
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#define CMDQ_EVENT_INI_FETCH_RDY 6
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#define CMDQ_EVENT_PROCESS_FLAG 7
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#define CMDQ_EVENT_SEARCH_START_CODE_DONE 8
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#define CMDQ_EVENT_REF_REORDER_DONE 9
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#define CMDQ_EVENT_WP_TBLE_DONE 10
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#define CMDQ_EVENT_COUNT_SRAM_CLR_DONE 11
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#define CMDQ_EVENT_GCE_CNT_OP_THRESHOLD 15
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_0 16
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_1 17
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_2 18
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_3 19
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_4 20
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_5 21
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_6 22
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_7 23
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_8 24
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_9 25
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_10 26
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_11 27
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_12 28
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_13 29
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_14 30
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#define CMDQ_EVENT_VDEC_MINI_MDP_EVENT_15 31
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#define CMDQ_EVENT_WPE_GCE_FRAME_DONE 32
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/* CAM */
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#define CMDQ_EVENT_ISP_FRAME_DONE_A 65
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#define CMDQ_EVENT_ISP_FRAME_DONE_B 66
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#define CMDQ_EVENT_CAMSV1_PASS1_DONE 70
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#define CMDQ_EVENT_CAMSV2_PASS1_DONE 71
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#define CMDQ_EVENT_CAMSV3_PASS1_DONE 72
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#define CMDQ_EVENT_MRAW_0_PASS1_DONE 73
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#define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 75
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#define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 76
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#define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 77
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#define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 78
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#define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 79
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#define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 80
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#define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 81
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#define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 82
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#define CMDQ_EVENT_SENINF_CAM8_FIFO_FULL 83
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#define CMDQ_EVENT_SENINF_CAM9_FIFO_FULL 84
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#define CMDQ_EVENT_SENINF_CAM10_FIFO_FULL 85
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#define CMDQ_EVENT_SENINF_CAM11_FIFO_FULL 86
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#define CMDQ_EVENT_SENINF_CAM12_FIFO_FULL 87
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#define CMDQ_EVENT_TG_OVRUN_A_INT 88
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#define CMDQ_EVENT_DMA_R1_ERROR_A_INT 89
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#define CMDQ_EVENT_TG_OVRUN_B_INT 90
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#define CMDQ_EVENT_DMA_R1_ERROR_B_INT 91
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#define CMDQ_EVENT_TG_OVRUN_M0_INT 94
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#define CMDQ_EVENT_R1_ERROR_M0_INT 95
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#define CMDQ_EVENT_TG_GRABERR_M0_INT 96
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#define CMDQ_EVENT_TG_GRABERR_A_INT 98
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#define CMDQ_EVENT_CQ_VR_SNAP_A_INT 99
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#define CMDQ_EVENT_TG_GRABERR_B_INT 100
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#define CMDQ_EVENT_CQ_VR_SNAP_B_INT 101
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/* VENC */
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#define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 129
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#define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 130
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#define CMDQ_EVENT_JPGENC_CMDQ_DONE 131
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#define CMDQ_EVENT_VENC_CMDQ_MB_DONE 132
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#define CMDQ_EVENT_VENC_CMDQ_128BYTE_CNT_DONE 133
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#define CMDQ_EVENT_VENC_CMDQ_PPS_DONE 136
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#define CMDQ_EVENT_VENC_CMDQ_SPS_DONE 137
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#define CMDQ_EVENT_VENC_CMDQ_VPS_DONE 138
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/* IPE */
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#define CMDQ_EVENT_FDVT_DONE 161
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#define CMDQ_EVENT_FE_DONE 162
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#define CMDQ_EVENT_RSC_DONE 163
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#define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 164
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#define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 165
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/* IMG2 */
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#define CMDQ_EVENT_GCE_IMG2_EVENT0 193
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#define CMDQ_EVENT_GCE_IMG2_EVENT1 194
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#define CMDQ_EVENT_GCE_IMG2_EVENT2 195
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#define CMDQ_EVENT_GCE_IMG2_EVENT3 196
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#define CMDQ_EVENT_GCE_IMG2_EVENT4 197
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#define CMDQ_EVENT_GCE_IMG2_EVENT5 198
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#define CMDQ_EVENT_GCE_IMG2_EVENT6 199
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#define CMDQ_EVENT_GCE_IMG2_EVENT7 200
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#define CMDQ_EVENT_GCE_IMG2_EVENT8 201
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#define CMDQ_EVENT_GCE_IMG2_EVENT9 202
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#define CMDQ_EVENT_GCE_IMG2_EVENT10 203
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#define CMDQ_EVENT_GCE_IMG2_EVENT11 204
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#define CMDQ_EVENT_GCE_IMG2_EVENT12 205
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#define CMDQ_EVENT_GCE_IMG2_EVENT13 206
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#define CMDQ_EVENT_GCE_IMG2_EVENT14 207
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#define CMDQ_EVENT_GCE_IMG2_EVENT15 208
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#define CMDQ_EVENT_GCE_IMG2_EVENT16 209
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#define CMDQ_EVENT_GCE_IMG2_EVENT17 210
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#define CMDQ_EVENT_GCE_IMG2_EVENT18 211
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#define CMDQ_EVENT_GCE_IMG2_EVENT19 212
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#define CMDQ_EVENT_GCE_IMG2_EVENT20 213
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#define CMDQ_EVENT_GCE_IMG2_EVENT21 214
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#define CMDQ_EVENT_GCE_IMG2_EVENT22 215
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#define CMDQ_EVENT_GCE_IMG2_EVENT23 216
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/* IMG1 */
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#define CMDQ_EVENT_GCE_IMG1_EVENT0 225
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#define CMDQ_EVENT_GCE_IMG1_EVENT1 226
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#define CMDQ_EVENT_GCE_IMG1_EVENT2 227
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#define CMDQ_EVENT_GCE_IMG1_EVENT3 228
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#define CMDQ_EVENT_GCE_IMG1_EVENT4 229
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#define CMDQ_EVENT_GCE_IMG1_EVENT5 230
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#define CMDQ_EVENT_GCE_IMG1_EVENT6 231
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#define CMDQ_EVENT_GCE_IMG1_EVENT7 232
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#define CMDQ_EVENT_GCE_IMG1_EVENT8 233
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#define CMDQ_EVENT_GCE_IMG1_EVENT9 234
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#define CMDQ_EVENT_GCE_IMG1_EVENT10 235
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#define CMDQ_EVENT_GCE_IMG1_EVENT11 236
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#define CMDQ_EVENT_GCE_IMG1_EVENT12 237
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#define CMDQ_EVENT_GCE_IMG1_EVENT13 238
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#define CMDQ_EVENT_GCE_IMG1_EVENT14 239
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#define CMDQ_EVENT_GCE_IMG1_EVENT15 240
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#define CMDQ_EVENT_GCE_IMG1_EVENT16 241
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#define CMDQ_EVENT_GCE_IMG1_EVENT17 242
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#define CMDQ_EVENT_GCE_IMG1_EVENT18 243
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#define CMDQ_EVENT_GCE_IMG1_EVENT19 244
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#define CMDQ_EVENT_GCE_IMG1_EVENT20 245
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#define CMDQ_EVENT_GCE_IMG1_EVENT21 246
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#define CMDQ_EVENT_GCE_IMG1_EVENT22 247
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#define CMDQ_EVENT_GCE_IMG1_EVENT23 248
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/* MDP */
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#define CMDQ_EVENT_MDP_RDMA0_SOF 256
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#define CMDQ_EVENT_MDP_RDMA1_SOF 257
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#define CMDQ_EVENT_MDP_AAL0_SOF 258
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#define CMDQ_EVENT_MDP_AAL1_SOF 259
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#define CMDQ_EVENT_MDP_HDR0_SOF 260
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#define CMDQ_EVENT_MDP_RSZ0_SOF 261
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#define CMDQ_EVENT_MDP_RSZ1_SOF 262
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#define CMDQ_EVENT_MDP_WROT0_SOF 263
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#define CMDQ_EVENT_MDP_WROT1_SOF 264
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#define CMDQ_EVENT_MDP_TDSHP0_SOF 265
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#define CMDQ_EVENT_MDP_TDSHP1_SOF 266
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#define CMDQ_EVENT_IMG_DL_RELAY0_SOF 267
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#define CMDQ_EVENT_IMG_DL_RELAY1_SOF 268
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#define CMDQ_EVENT_MDP_COLOR0_SOF 269
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#define CMDQ_EVENT_MDP_WROT3_FRAME_DONE 288
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#define CMDQ_EVENT_MDP_WROT2_FRAME_DONE 289
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#define CMDQ_EVENT_MDP_WROT1_FRAME_DONE 290
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#define CMDQ_EVENT_MDP_WROT0_FRAME_DONE 291
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#define CMDQ_EVENT_MDP_TDSHP3_FRAME_DONE 292
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#define CMDQ_EVENT_MDP_TDSHP2_FRAME_DONE 293
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#define CMDQ_EVENT_MDP_TDSHP1_FRAME_DONE 294
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#define CMDQ_EVENT_MDP_TDSHP0_FRAME_DONE 295
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#define CMDQ_EVENT_MDP_RSZ3_FRAME_DONE 296
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#define CMDQ_EVENT_MDP_RSZ2_FRAME_DONE 297
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#define CMDQ_EVENT_MDP_RSZ1_FRAME_DONE 298
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#define CMDQ_EVENT_MDP_RSZ0_FRAME_DONE 299
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#define CMDQ_EVENT_MDP_RDMA3_FRAME_DONE 300
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#define CMDQ_EVENT_MDP_RDMA2_FRAME_DONE 301
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#define CMDQ_EVENT_MDP_RDMA1_FRAME_DONE 302
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#define CMDQ_EVENT_MDP_RDMA0_FRAME_DONE 303
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#define CMDQ_EVENT_MDP_HDR1_FRAME_DONE 304
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#define CMDQ_EVENT_MDP_HDR0_FRAME_DONE 305
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#define CMDQ_EVENT_MDP_COLOR0_FRAME_DONE 306
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#define CMDQ_EVENT_MDP_AAL3_FRAME_DONE 307
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#define CMDQ_EVENT_MDP_AAL2_FRAME_DONE 308
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#define CMDQ_EVENT_MDP_AAL1_FRAME_DONE 309
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#define CMDQ_EVENT_MDP_AAL0_FRAME_DONE 310
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_0 320
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_1 321
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_2 322
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_3 323
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_4 324
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_5 325
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_6 326
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_7 327
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_8 328
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_9 329
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_10 330
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_11 331
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_12 332
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_13 333
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_14 334
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#define CMDQ_EVENT_MDP_STREAM_DONE_ENG_EVENT_15 335
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#define CMDQ_EVENT_MDP_WROT3_SW_RST_DONE_ENG_EVENT 336
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#define CMDQ_EVENT_MDP_WROT2_SW_RST_DONE_ENG_EVENT 337
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#define CMDQ_EVENT_MDP_WROT1_SW_RST_DONE_ENG_EVENT 338
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#define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE_ENG_EVENT 339
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#define CMDQ_EVENT_MDP_RDMA3_SW_RST_DONE_ENG_EVENT 340
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#define CMDQ_EVENT_MDP_RDMA2_SW_RST_DONE_ENG_EVENT 341
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#define CMDQ_EVENT_MDP_RDMA1_SW_RST_DONE_ENG_EVENT 342
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#define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE_ENG_EVENT 343
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/* DISP */
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#define CMDQ_EVENT_DISP_OVL0_SOF 384
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#define CMDQ_EVENT_DISP_OVL0_2L_SOF 385
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#define CMDQ_EVENT_DISP_RDMA0_SOF 386
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#define CMDQ_EVENT_DISP_RSZ0_SOF 387
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#define CMDQ_EVENT_DISP_COLOR0_SOF 388
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#define CMDQ_EVENT_DISP_CCORR0_SOF 389
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#define CMDQ_EVENT_DISP_CCORR1_SOF 390
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#define CMDQ_EVENT_DISP_AAL0_SOF 391
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#define CMDQ_EVENT_DISP_GAMMA0_SOF 392
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#define CMDQ_EVENT_DISP_POSTMASK0_SOF 393
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#define CMDQ_EVENT_DISP_DITHER0_SOF 394
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#define CMDQ_EVENT_DISP_CM0_SOF 395
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#define CMDQ_EVENT_DISP_SPR0_SOF 396
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#define CMDQ_EVENT_DISP_DSC_WRAP0_SOF 397
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#define CMDQ_EVENT_DSI0_SOF 398
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#define CMDQ_EVENT_DISP_WDMA0_SOF 399
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#define CMDQ_EVENT_DISP_PWM0_SOF 400
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#define CMDQ_EVENT_DSI0_FRAME_DONE 410
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#define CMDQ_EVENT_DISP_WDMA0_FRAME_DONE 411
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#define CMDQ_EVENT_DISP_SPR0_FRAME_DONE 412
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#define CMDQ_EVENT_DISP_RSZ0_FRAME_DONE 413
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#define CMDQ_EVENT_DISP_RDMA0_FRAME_DONE 414
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#define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 415
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#define CMDQ_EVENT_DISP_OVL0_FRAME_DONE 416
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#define CMDQ_EVENT_DISP_OVL0_2L_FRAME_DONE 417
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#define CMDQ_EVENT_DISP_GAMMA0_FRAME_DONE 418
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#define CMDQ_EVENT_DISP_DSC_WRAP0_CORE0_FRAME_DONE 420
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#define CMDQ_EVENT_DISP_DITHER0_FRAME_DONE 421
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#define CMDQ_EVENT_DISP_COLOR0_FRAME_DONE 422
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#define CMDQ_EVENT_DISP_CM0_FRAME_DONE 423
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#define CMDQ_EVENT_DISP_CCORR1_FRAME_DONE 424
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#define CMDQ_EVENT_DISP_CCORR0_FRAME_DONE 425
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#define CMDQ_EVENT_DISP_AAL0_FRAME_DONE 426
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0 434
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1 435
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_2 436
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||
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_3 437
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||
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_4 438
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||
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_5 439
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||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_6 440
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||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_7 441
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_8 442
|
||
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_9 443
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_10 444
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_11 445
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_12 446
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_13 447
|
||
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_14 448
|
||
|
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#define CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_15 449
|
||
|
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#define CMDQ_EVENT_DSI0_TE_ENG_EVENT 450
|
||
|
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#define CMDQ_EVENT_DSI0_IRQ_ENG_EVENT 451
|
||
|
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#define CMDQ_EVENT_DSI0_DONE_ENG_EVENT 452
|
||
|
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#define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE_ENG_EVENT 453
|
||
|
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#define CMDQ_EVENT_DISP_SMIASSERT_ENG_EVENT 454
|
||
|
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#define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE_ENG_EVENT 455
|
||
|
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#define CMDQ_EVENT_DISP_OVL0_RST_DONE_ENG_EVENT 456
|
||
|
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#define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE_ENG_EVENT 457
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_0 458
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_1 459
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_2 460
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_3 461
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_4 462
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_5 463
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_6 464
|
||
|
|
#define CMDQ_EVENT_BUF_UNDERRUN_ENG_EVENT_7 465
|
||
|
|
#define CMDQ_EVENT_OUT_EVENT_0 898
|
||
|
|
|
||
|
|
/* CMDQ sw tokens
|
||
|
|
* Following definitions are gce sw token which may use by clients
|
||
|
|
* event operation API.
|
||
|
|
* Note that token 512 to 639 may set secure
|
||
|
|
*/
|
||
|
|
|
||
|
|
/* end of hw event and begin of sw token */
|
||
|
|
#define CMDQ_MAX_HW_EVENT 512
|
||
|
|
|
||
|
|
/* Config thread notify trigger thread */
|
||
|
|
#define CMDQ_SYNC_TOKEN_CONFIG_DIRTY 640
|
||
|
|
/* Trigger thread notify config thread */
|
||
|
|
#define CMDQ_SYNC_TOKEN_STREAM_EOF 641
|
||
|
|
/* Block Trigger thread until the ESD check finishes. */
|
||
|
|
#define CMDQ_SYNC_TOKEN_ESD_EOF 642
|
||
|
|
#define CMDQ_SYNC_TOKEN_STREAM_BLOCK 643
|
||
|
|
/* check CABC setup finish */
|
||
|
|
#define CMDQ_SYNC_TOKEN_CABC_EOF 644
|
||
|
|
|
||
|
|
/* Notify normal CMDQ there are some secure task done
|
||
|
|
* MUST NOT CHANGE, this token sync with secure world
|
||
|
|
*/
|
||
|
|
#define CMDQ_SYNC_SECURE_THR_EOF 647
|
||
|
|
|
||
|
|
/* CMDQ use sw token */
|
||
|
|
#define CMDQ_SYNC_TOKEN_USER_0 649
|
||
|
|
#define CMDQ_SYNC_TOKEN_USER_1 650
|
||
|
|
#define CMDQ_SYNC_TOKEN_POLL_MONITOR 651
|
||
|
|
#define CMDQ_SYNC_TOKEN_TPR_LOCK 652
|
||
|
|
|
||
|
|
/* ISP sw token */
|
||
|
|
#define CMDQ_SYNC_TOKEN_MSS 665
|
||
|
|
#define CMDQ_SYNC_TOKEN_MSF 666
|
||
|
|
|
||
|
|
/* DISP sw token */
|
||
|
|
#define CMDQ_SYNC_TOKEN_SODI 671
|
||
|
|
|
||
|
|
/* GPR access tokens (for register backup)
|
||
|
|
* There are 15 32-bit GPR, 3 GPR form a set
|
||
|
|
* (64-bit for address, 32-bit for value)
|
||
|
|
* MUST NOT CHANGE, these tokens sync with MDP
|
||
|
|
*/
|
||
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_0 700
|
||
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_1 701
|
||
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_2 702
|
||
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_3 703
|
||
|
|
#define CMDQ_SYNC_TOKEN_GPR_SET_4 704
|
||
|
|
|
||
|
|
/* Resource lock event to control resource in GCE thread */
|
||
|
|
#define CMDQ_SYNC_RESOURCE_WROT0 710
|
||
|
|
#define CMDQ_SYNC_RESOURCE_WROT1 711
|
||
|
|
|
||
|
|
/* event for gpr timer, used in sleep and poll with timeout */
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R0 994
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R1 995
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R2 996
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R3 997
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R4 998
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R5 999
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R6 1000
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R7 1001
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R8 1002
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R9 1003
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R10 1004
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R11 1005
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R12 1006
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R13 1007
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R14 1008
|
||
|
|
#define CMDQ_TOKEN_GPR_TIMER_R15 1009
|
||
|
|
|
||
|
|
#define CMDQ_EVENT_MAX 0x3FF
|
||
|
|
/* CMDQ sw tokens END */
|
||
|
|
|
||
|
|
#endif
|