18 lines
426 B
C
18 lines
426 B
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* MIO pin configuration defines for Xilinx Zynq
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*
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* Copyright (C) 2021 Xilinx, Inc.
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*/
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#ifndef _DT_BINDINGS_PINCTRL_ZYNQ_H
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#define _DT_BINDINGS_PINCTRL_ZYNQ_H
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/* Configuration options for different power supplies */
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#define IO_STANDARD_LVCMOS18 1
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#define IO_STANDARD_LVCMOS25 2
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#define IO_STANDARD_LVCMOS33 3
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#define IO_STANDARD_HSTL 4
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#endif /* _DT_BINDINGS_PINCTRL_ZYNQ_H */
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