180 lines
7.2 KiB
C
180 lines
7.2 KiB
C
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/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Sunplus SP7021 dt-bindings Pinctrl header file
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* Copyright (C) Sunplus Tech/Tibbo Tech.
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* Author: Dvorkin Dmitry <dvorkin@tibbo.com>
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*/
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#ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
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#define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__
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#include <dt-bindings/pinctrl/sppctl.h>
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/*
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* Please don't change the order of the following defines.
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* They are based on order of 'hardware' control register
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* defined in MOON2 ~ MOON3 registers.
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*/
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#define MUXF_GPIO 0
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#define MUXF_IOP 1
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#define MUXF_L2SW_CLK_OUT 2
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#define MUXF_L2SW_MAC_SMI_MDC 3
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#define MUXF_L2SW_LED_FLASH0 4
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#define MUXF_L2SW_LED_FLASH1 5
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#define MUXF_L2SW_LED_ON0 6
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#define MUXF_L2SW_LED_ON1 7
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#define MUXF_L2SW_MAC_SMI_MDIO 8
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#define MUXF_L2SW_P0_MAC_RMII_TXEN 9
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#define MUXF_L2SW_P0_MAC_RMII_TXD0 10
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#define MUXF_L2SW_P0_MAC_RMII_TXD1 11
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#define MUXF_L2SW_P0_MAC_RMII_CRSDV 12
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#define MUXF_L2SW_P0_MAC_RMII_RXD0 13
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#define MUXF_L2SW_P0_MAC_RMII_RXD1 14
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#define MUXF_L2SW_P0_MAC_RMII_RXER 15
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#define MUXF_L2SW_P1_MAC_RMII_TXEN 16
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#define MUXF_L2SW_P1_MAC_RMII_TXD0 17
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#define MUXF_L2SW_P1_MAC_RMII_TXD1 18
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#define MUXF_L2SW_P1_MAC_RMII_CRSDV 19
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#define MUXF_L2SW_P1_MAC_RMII_RXD0 20
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#define MUXF_L2SW_P1_MAC_RMII_RXD1 21
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#define MUXF_L2SW_P1_MAC_RMII_RXER 22
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#define MUXF_DAISY_MODE 23
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#define MUXF_SDIO_CLK 24
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#define MUXF_SDIO_CMD 25
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#define MUXF_SDIO_D0 26
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#define MUXF_SDIO_D1 27
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#define MUXF_SDIO_D2 28
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#define MUXF_SDIO_D3 29
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#define MUXF_PWM0 30
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#define MUXF_PWM1 31
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#define MUXF_PWM2 32
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#define MUXF_PWM3 33
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#define MUXF_PWM4 34
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#define MUXF_PWM5 35
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#define MUXF_PWM6 36
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#define MUXF_PWM7 37
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#define MUXF_ICM0_D 38
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#define MUXF_ICM1_D 39
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#define MUXF_ICM2_D 40
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#define MUXF_ICM3_D 41
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#define MUXF_ICM0_CLK 42
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#define MUXF_ICM1_CLK 43
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#define MUXF_ICM2_CLK 44
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#define MUXF_ICM3_CLK 45
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#define MUXF_SPIM0_INT 46
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#define MUXF_SPIM0_CLK 47
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#define MUXF_SPIM0_EN 48
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#define MUXF_SPIM0_DO 49
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#define MUXF_SPIM0_DI 50
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#define MUXF_SPIM1_INT 51
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#define MUXF_SPIM1_CLK 52
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#define MUXF_SPIM1_EN 53
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#define MUXF_SPIM1_DO 54
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#define MUXF_SPIM1_DI 55
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#define MUXF_SPIM2_INT 56
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#define MUXF_SPIM2_CLK 57
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#define MUXF_SPIM2_EN 58
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#define MUXF_SPIM2_DO 59
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#define MUXF_SPIM2_DI 60
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#define MUXF_SPIM3_INT 61
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#define MUXF_SPIM3_CLK 62
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#define MUXF_SPIM3_EN 63
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#define MUXF_SPIM3_DO 64
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#define MUXF_SPIM3_DI 65
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#define MUXF_SPI0S_INT 66
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#define MUXF_SPI0S_CLK 67
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#define MUXF_SPI0S_EN 68
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#define MUXF_SPI0S_DO 69
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#define MUXF_SPI0S_DI 70
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#define MUXF_SPI1S_INT 71
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#define MUXF_SPI1S_CLK 72
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#define MUXF_SPI1S_EN 73
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#define MUXF_SPI1S_DO 74
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#define MUXF_SPI1S_DI 75
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#define MUXF_SPI2S_INT 76
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#define MUXF_SPI2S_CLK 77
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#define MUXF_SPI2S_EN 78
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#define MUXF_SPI2S_DO 79
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#define MUXF_SPI2S_DI 80
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#define MUXF_SPI3S_INT 81
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#define MUXF_SPI3S_CLK 82
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#define MUXF_SPI3S_EN 83
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#define MUXF_SPI3S_DO 84
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#define MUXF_SPI3S_DI 85
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#define MUXF_I2CM0_CLK 86
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#define MUXF_I2CM0_DAT 87
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#define MUXF_I2CM1_CLK 88
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#define MUXF_I2CM1_DAT 89
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#define MUXF_I2CM2_CLK 90
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#define MUXF_I2CM2_DAT 91
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#define MUXF_I2CM3_CLK 92
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#define MUXF_I2CM3_DAT 93
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#define MUXF_UA1_TX 94
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#define MUXF_UA1_RX 95
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#define MUXF_UA1_CTS 96
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#define MUXF_UA1_RTS 97
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#define MUXF_UA2_TX 98
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#define MUXF_UA2_RX 99
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#define MUXF_UA2_CTS 100
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#define MUXF_UA2_RTS 101
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#define MUXF_UA3_TX 102
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#define MUXF_UA3_RX 103
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#define MUXF_UA3_CTS 104
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#define MUXF_UA3_RTS 105
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#define MUXF_UA4_TX 106
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#define MUXF_UA4_RX 107
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#define MUXF_UA4_CTS 108
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#define MUXF_UA4_RTS 109
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#define MUXF_TIMER0_INT 110
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#define MUXF_TIMER1_INT 111
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#define MUXF_TIMER2_INT 112
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#define MUXF_TIMER3_INT 113
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#define MUXF_GPIO_INT0 114
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#define MUXF_GPIO_INT1 115
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#define MUXF_GPIO_INT2 116
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#define MUXF_GPIO_INT3 117
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#define MUXF_GPIO_INT4 118
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#define MUXF_GPIO_INT5 119
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#define MUXF_GPIO_INT6 120
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#define MUXF_GPIO_INT7 121
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/*
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* Please don't change the order of the following defines.
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* They are based on order of items in array 'sppctl_list_funcs'
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* in Sunplus pinctrl driver.
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*/
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#define GROP_SPI_FLASH 122
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#define GROP_SPI_FLASH_4BIT 123
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#define GROP_SPI_NAND 124
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#define GROP_CARD0_EMMC 125
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#define GROP_SD_CARD 126
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#define GROP_UA0 127
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#define GROP_ACHIP_DEBUG 128
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#define GROP_ACHIP_UA2AXI 129
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#define GROP_FPGA_IFX 130
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#define GROP_HDMI_TX 131
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#define GROP_AUD_EXT_ADC_IFX0 132
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#define GROP_AUD_EXT_DAC_IFX0 133
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#define GROP_SPDIF_RX 134
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#define GROP_SPDIF_TX 135
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#define GROP_TDMTX_IFX0 136
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#define GROP_TDMRX_IFX0 137
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#define GROP_PDMRX_IFX0 138
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#define GROP_PCM_IEC_TX 139
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#define GROP_LCDIF 140
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#define GROP_DVD_DSP_DEBUG 141
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#define GROP_I2C_DEBUG 142
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#define GROP_I2C_SLAVE 143
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#define GROP_WAKEUP 144
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#define GROP_UART2AXI 145
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#define GROP_USB0_I2C 146
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#define GROP_USB1_I2C 147
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#define GROP_USB0_OTG 148
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#define GROP_USB1_OTG 149
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#define GROP_UPHY0_DEBUG 150
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#define GROP_UPHY1_DEBUG 151
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#define GROP_UPHY0_EXT 152
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#define GROP_PROBE_PORT 153
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#endif
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