147 lines
5.4 KiB
C
147 lines
5.4 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com
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*/
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#ifndef K3_UDMA_GLUE_H_
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#define K3_UDMA_GLUE_H_
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#include <linux/types.h>
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#include <linux/soc/ti/k3-ringacc.h>
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#include <linux/dma/ti-cppi5.h>
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struct k3_udma_glue_tx_channel_cfg {
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struct k3_ring_cfg tx_cfg;
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struct k3_ring_cfg txcq_cfg;
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bool tx_pause_on_err;
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bool tx_filt_einfo;
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bool tx_filt_pswords;
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bool tx_supr_tdpkt;
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u32 swdata_size;
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};
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struct k3_udma_glue_tx_channel;
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struct k3_udma_glue_tx_channel *k3_udma_glue_request_tx_chn(struct device *dev,
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const char *name, struct k3_udma_glue_tx_channel_cfg *cfg);
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void k3_udma_glue_release_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
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int k3_udma_glue_push_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
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struct cppi5_host_desc_t *desc_tx,
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dma_addr_t desc_dma);
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int k3_udma_glue_pop_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
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dma_addr_t *desc_dma);
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int k3_udma_glue_enable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
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void k3_udma_glue_disable_tx_chn(struct k3_udma_glue_tx_channel *tx_chn);
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void k3_udma_glue_tdown_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
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bool sync);
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void k3_udma_glue_reset_tx_chn(struct k3_udma_glue_tx_channel *tx_chn,
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void *data, void (*cleanup)(void *data, dma_addr_t desc_dma));
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u32 k3_udma_glue_tx_get_hdesc_size(struct k3_udma_glue_tx_channel *tx_chn);
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u32 k3_udma_glue_tx_get_txcq_id(struct k3_udma_glue_tx_channel *tx_chn);
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int k3_udma_glue_tx_get_irq(struct k3_udma_glue_tx_channel *tx_chn);
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struct device *
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k3_udma_glue_tx_get_dma_device(struct k3_udma_glue_tx_channel *tx_chn);
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void k3_udma_glue_tx_dma_to_cppi5_addr(struct k3_udma_glue_tx_channel *tx_chn,
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dma_addr_t *addr);
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void k3_udma_glue_tx_cppi5_to_dma_addr(struct k3_udma_glue_tx_channel *tx_chn,
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dma_addr_t *addr);
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enum {
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K3_UDMA_GLUE_SRC_TAG_LO_KEEP = 0,
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K3_UDMA_GLUE_SRC_TAG_LO_USE_FLOW_REG = 1,
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K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_FLOW_ID = 2,
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K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG = 4,
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};
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/**
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* k3_udma_glue_rx_flow_cfg - UDMA RX flow cfg
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*
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* @rx_cfg: RX ring configuration
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* @rxfdq_cfg: RX free Host PD ring configuration
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* @ring_rxq_id: RX ring id (or -1 for any)
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* @ring_rxfdq0_id: RX free Host PD ring (FDQ) if (or -1 for any)
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* @rx_error_handling: Rx Error Handling Mode (0 - drop, 1 - re-try)
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* @src_tag_lo_sel: Rx Source Tag Low Byte Selector in Host PD
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*/
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struct k3_udma_glue_rx_flow_cfg {
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struct k3_ring_cfg rx_cfg;
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struct k3_ring_cfg rxfdq_cfg;
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int ring_rxq_id;
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int ring_rxfdq0_id;
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bool rx_error_handling;
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int src_tag_lo_sel;
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};
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/**
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* k3_udma_glue_rx_channel_cfg - UDMA RX channel cfg
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*
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* @psdata_size: SW Data is present in Host PD of @swdata_size bytes
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* @flow_id_base: first flow_id used by channel.
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* if @flow_id_base = -1 - range of GP rflows will be
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* allocated dynamically.
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* @flow_id_num: number of RX flows used by channel
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* @flow_id_use_rxchan_id: use RX channel id as flow id,
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* used only if @flow_id_num = 1
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* @remote indication that RX channel is remote - some remote CPU
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* core owns and control the RX channel. Linux Host only
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* allowed to attach and configure RX Flow within RX
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* channel. if set - not RX channel operation will be
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* performed by K3 NAVSS DMA glue interface.
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* @def_flow_cfg default RX flow configuration,
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* used only if @flow_id_num = 1
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*/
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struct k3_udma_glue_rx_channel_cfg {
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u32 swdata_size;
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int flow_id_base;
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int flow_id_num;
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bool flow_id_use_rxchan_id;
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bool remote;
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struct k3_udma_glue_rx_flow_cfg *def_flow_cfg;
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};
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struct k3_udma_glue_rx_channel;
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struct k3_udma_glue_rx_channel *k3_udma_glue_request_rx_chn(
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struct device *dev,
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const char *name,
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struct k3_udma_glue_rx_channel_cfg *cfg);
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void k3_udma_glue_release_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
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int k3_udma_glue_enable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
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void k3_udma_glue_disable_rx_chn(struct k3_udma_glue_rx_channel *rx_chn);
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void k3_udma_glue_tdown_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
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bool sync);
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int k3_udma_glue_push_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_num, struct cppi5_host_desc_t *desc_tx,
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dma_addr_t desc_dma);
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int k3_udma_glue_pop_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_num, dma_addr_t *desc_dma);
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int k3_udma_glue_rx_flow_init(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_idx, struct k3_udma_glue_rx_flow_cfg *flow_cfg);
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u32 k3_udma_glue_rx_flow_get_fdq_id(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_idx);
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u32 k3_udma_glue_rx_get_flow_id_base(struct k3_udma_glue_rx_channel *rx_chn);
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int k3_udma_glue_rx_get_irq(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_num);
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void k3_udma_glue_rx_put_irq(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_num);
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void k3_udma_glue_reset_rx_chn(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_num, void *data,
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void (*cleanup)(void *data, dma_addr_t desc_dma),
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bool skip_fdq);
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int k3_udma_glue_rx_flow_enable(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_idx);
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int k3_udma_glue_rx_flow_disable(struct k3_udma_glue_rx_channel *rx_chn,
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u32 flow_idx);
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struct device *
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k3_udma_glue_rx_get_dma_device(struct k3_udma_glue_rx_channel *rx_chn);
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void k3_udma_glue_rx_dma_to_cppi5_addr(struct k3_udma_glue_rx_channel *rx_chn,
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dma_addr_t *addr);
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void k3_udma_glue_rx_cppi5_to_dma_addr(struct k3_udma_glue_rx_channel *rx_chn,
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dma_addr_t *addr);
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#endif /* K3_UDMA_GLUE_H_ */
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