116 lines
3.0 KiB
C
116 lines
3.0 KiB
C
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Register Map - Based on AN888_SMUforIEEE_SynchEther_82P33xxx_RevH.pdf
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*
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* Copyright (C) 2021 Integrated Device Technology, Inc., a Renesas Company.
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*/
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#ifndef HAVE_IDT82P33_REG
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#define HAVE_IDT82P33_REG
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#define REG_ADDR(page, offset) (((page) << 0x7) | ((offset) & 0x7f))
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/* Register address */
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#define DPLL1_TOD_CNFG 0x134
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#define DPLL2_TOD_CNFG 0x1B4
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#define DPLL1_TOD_STS 0x10B
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#define DPLL2_TOD_STS 0x18B
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#define DPLL1_TOD_TRIGGER 0x115
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#define DPLL2_TOD_TRIGGER 0x195
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#define DPLL1_OPERATING_MODE_CNFG 0x120
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#define DPLL2_OPERATING_MODE_CNFG 0x1A0
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#define DPLL1_HOLDOVER_FREQ_CNFG 0x12C
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#define DPLL2_HOLDOVER_FREQ_CNFG 0x1AC
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#define DPLL1_PHASE_OFFSET_CNFG 0x143
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#define DPLL2_PHASE_OFFSET_CNFG 0x1C3
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#define DPLL1_SYNC_EDGE_CNFG 0x140
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#define DPLL2_SYNC_EDGE_CNFG 0x1C0
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#define DPLL1_INPUT_MODE_CNFG 0x116
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#define DPLL2_INPUT_MODE_CNFG 0x196
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#define DPLL1_OPERATING_STS 0x102
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#define DPLL2_OPERATING_STS 0x182
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#define DPLL1_CURRENT_FREQ_STS 0x103
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#define DPLL2_CURRENT_FREQ_STS 0x183
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#define REG_SOFT_RESET 0X381
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#define OUT_MUX_CNFG(outn) REG_ADDR(0x6, (0xC * (outn)))
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#define TOD_TRIGGER(wr_trig, rd_trig) ((wr_trig & 0xf) << 4 | (rd_trig & 0xf))
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/* Register bit definitions */
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#define SYNC_TOD BIT(1)
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#define PH_OFFSET_EN BIT(7)
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#define SQUELCH_ENABLE BIT(5)
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/* Bit definitions for the DPLL_MODE register */
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#define PLL_MODE_SHIFT (0)
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#define PLL_MODE_MASK (0x1F)
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#define COMBO_MODE_EN BIT(5)
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#define COMBO_MODE_SHIFT (6)
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#define COMBO_MODE_MASK (0x3)
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/* Bit definitions for DPLL_OPERATING_STS register */
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#define OPERATING_STS_MASK (0x7)
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#define OPERATING_STS_SHIFT (0x0)
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/* Bit definitions for DPLL_TOD_TRIGGER register */
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#define READ_TRIGGER_MASK (0xF)
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#define READ_TRIGGER_SHIFT (0x0)
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#define WRITE_TRIGGER_MASK (0xF0)
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#define WRITE_TRIGGER_SHIFT (0x4)
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/* Bit definitions for REG_SOFT_RESET register */
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#define SOFT_RESET_EN BIT(7)
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enum pll_mode {
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PLL_MODE_MIN = 0,
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PLL_MODE_AUTOMATIC = PLL_MODE_MIN,
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PLL_MODE_FORCE_FREERUN = 1,
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PLL_MODE_FORCE_HOLDOVER = 2,
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PLL_MODE_FORCE_LOCKED = 4,
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PLL_MODE_FORCE_PRE_LOCKED2 = 5,
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PLL_MODE_FORCE_PRE_LOCKED = 6,
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PLL_MODE_FORCE_LOST_PHASE = 7,
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PLL_MODE_DCO = 10,
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PLL_MODE_WPH = 18,
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PLL_MODE_MAX = PLL_MODE_WPH,
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};
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enum hw_tod_trig_sel {
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HW_TOD_TRIG_SEL_MIN = 0,
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HW_TOD_TRIG_SEL_NO_WRITE = HW_TOD_TRIG_SEL_MIN,
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HW_TOD_TRIG_SEL_NO_READ = HW_TOD_TRIG_SEL_MIN,
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HW_TOD_TRIG_SEL_SYNC_SEL = 1,
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HW_TOD_TRIG_SEL_IN12 = 2,
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HW_TOD_TRIG_SEL_IN13 = 3,
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HW_TOD_TRIG_SEL_IN14 = 4,
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HW_TOD_TRIG_SEL_TOD_PPS = 5,
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HW_TOD_TRIG_SEL_TIMER_INTERVAL = 6,
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HW_TOD_TRIG_SEL_MSB_PHASE_OFFSET_CNFG = 7,
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HW_TOD_TRIG_SEL_MSB_HOLDOVER_FREQ_CNFG = 8,
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HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG = 9,
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HW_TOD_RD_TRIG_SEL_LSB_TOD_STS = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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WR_TRIG_SEL_MAX = HW_TOD_WR_TRIG_SEL_MSB_TOD_CNFG,
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};
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/** @brief Enumerated type listing DPLL operational modes */
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enum dpll_state {
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DPLL_STATE_FREERUN = 1,
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DPLL_STATE_HOLDOVER = 2,
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DPLL_STATE_LOCKED = 4,
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DPLL_STATE_PRELOCKED2 = 5,
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DPLL_STATE_PRELOCKED = 6,
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DPLL_STATE_LOSTPHASE = 7,
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DPLL_STATE_MAX
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};
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#endif
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