369 lines
10 KiB
C
369 lines
10 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* skl-sst-cldma.c - Code Loader DMA handler
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*
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* Copyright (C) 2015, Intel Corporation.
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* Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/delay.h>
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#include "../common/sst-dsp.h"
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#include "../common/sst-dsp-priv.h"
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static void skl_cldma_int_enable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx, SKL_ADSP_REG_ADSPIC,
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SKL_ADSPIC_CL_DMA, SKL_ADSPIC_CL_DMA);
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}
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void skl_cldma_int_disable(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_ADSPIC, SKL_ADSPIC_CL_DMA, 0);
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}
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static void skl_cldma_stream_run(struct sst_dsp *ctx, bool enable)
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{
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unsigned char val;
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int timeout;
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_RUN_MASK, CL_SD_CTL_RUN(enable));
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udelay(3);
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timeout = 300;
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do {
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/* waiting for hardware to report that the stream Run bit set */
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val = sst_dsp_shim_read(ctx, SKL_ADSP_REG_CL_SD_CTL) &
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CL_SD_CTL_RUN_MASK;
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if (enable && val)
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break;
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else if (!enable && !val)
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break;
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udelay(3);
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} while (--timeout);
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if (timeout == 0)
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dev_err(ctx->dev, "Failed to set Run bit=%d enable=%d\n", val, enable);
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}
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static void skl_cldma_stream_clear(struct sst_dsp *ctx)
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{
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/* make sure Run bit is cleared before setting stream register */
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skl_cldma_stream_run(ctx, 0);
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(0));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(0));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL, CL_SD_BDLPLBA(0));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU, 0);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, 0);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, 0);
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}
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/* Code loader helper APIs */
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static void skl_cldma_setup_bdle(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_data,
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__le32 **bdlp, int size, int with_ioc)
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{
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__le32 *bdl = *bdlp;
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ctx->cl_dev.frags = 0;
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while (size > 0) {
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phys_addr_t addr = virt_to_phys(dmab_data->area +
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(ctx->cl_dev.frags * ctx->cl_dev.bufsize));
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bdl[0] = cpu_to_le32(lower_32_bits(addr));
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bdl[1] = cpu_to_le32(upper_32_bits(addr));
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bdl[2] = cpu_to_le32(ctx->cl_dev.bufsize);
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size -= ctx->cl_dev.bufsize;
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bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
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bdl += 4;
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ctx->cl_dev.frags++;
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}
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}
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/*
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* Setup controller
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* Configure the registers to update the dma buffer address and
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* enable interrupts.
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* Note: Using the channel 1 for transfer
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*/
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static void skl_cldma_setup_controller(struct sst_dsp *ctx,
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struct snd_dma_buffer *dmab_bdl, unsigned int max_size,
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u32 count)
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{
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skl_cldma_stream_clear(ctx);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPL,
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CL_SD_BDLPLBA(dmab_bdl->addr));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_BDLPU,
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CL_SD_BDLPUBA(dmab_bdl->addr));
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_CBL, max_size);
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sst_dsp_shim_write(ctx, SKL_ADSP_REG_CL_SD_LVI, count - 1);
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_IOCE_MASK, CL_SD_CTL_IOCE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_FEIE_MASK, CL_SD_CTL_FEIE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_DEIE_MASK, CL_SD_CTL_DEIE(1));
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sst_dsp_shim_update_bits(ctx, SKL_ADSP_REG_CL_SD_CTL,
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CL_SD_CTL_STRM_MASK, CL_SD_CTL_STRM(FW_CL_STREAM_NUMBER));
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}
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static void skl_cldma_setup_spb(struct sst_dsp *ctx,
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unsigned int size, bool enable)
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{
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if (enable)
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
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CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
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CL_SPBFIFO_SPBFCCTL_SPIBE(1));
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sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, size);
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}
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static void skl_cldma_cleanup_spb(struct sst_dsp *ctx)
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{
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sst_dsp_shim_update_bits_unlocked(ctx,
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SKL_ADSP_REG_CL_SPBFIFO_SPBFCCTL,
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CL_SPBFIFO_SPBFCCTL_SPIBE_MASK,
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CL_SPBFIFO_SPBFCCTL_SPIBE(0));
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sst_dsp_shim_write_unlocked(ctx, SKL_ADSP_REG_CL_SPBFIFO_SPIB, 0);
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}
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static void skl_cldma_cleanup(struct sst_dsp *ctx)
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{
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skl_cldma_cleanup_spb(ctx);
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skl_cldma_stream_clear(ctx);
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ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
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ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_bdl);
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}
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int skl_cldma_wait_interruptible(struct sst_dsp *ctx)
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{
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int ret = 0;
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if (!wait_event_timeout(ctx->cl_dev.wait_queue,
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ctx->cl_dev.wait_condition,
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msecs_to_jiffies(SKL_WAIT_TIMEOUT))) {
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dev_err(ctx->dev, "%s: Wait timeout\n", __func__);
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ret = -EIO;
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goto cleanup;
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}
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dev_dbg(ctx->dev, "%s: Event wake\n", __func__);
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if (ctx->cl_dev.wake_status != SKL_CL_DMA_BUF_COMPLETE) {
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dev_err(ctx->dev, "%s: DMA Error\n", __func__);
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ret = -EIO;
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}
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cleanup:
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ctx->cl_dev.wake_status = SKL_CL_DMA_STATUS_NONE;
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return ret;
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}
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static void skl_cldma_stop(struct sst_dsp *ctx)
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{
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skl_cldma_stream_run(ctx, false);
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}
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static void skl_cldma_fill_buffer(struct sst_dsp *ctx, unsigned int size,
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const void *curr_pos, bool intr_enable, bool trigger)
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{
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dev_dbg(ctx->dev, "Size: %x, intr_enable: %d\n", size, intr_enable);
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dev_dbg(ctx->dev, "buf_pos_index:%d, trigger:%d\n",
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ctx->cl_dev.dma_buffer_offset, trigger);
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dev_dbg(ctx->dev, "spib position: %d\n", ctx->cl_dev.curr_spib_pos);
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/*
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* Check if the size exceeds buffer boundary. If it exceeds
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* max_buffer size, then copy till buffer size and then copy
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* remaining buffer from the start of ring buffer.
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*/
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if (ctx->cl_dev.dma_buffer_offset + size > ctx->cl_dev.bufsize) {
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unsigned int size_b = ctx->cl_dev.bufsize -
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ctx->cl_dev.dma_buffer_offset;
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memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
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curr_pos, size_b);
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size -= size_b;
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curr_pos += size_b;
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ctx->cl_dev.dma_buffer_offset = 0;
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}
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memcpy(ctx->cl_dev.dmab_data.area + ctx->cl_dev.dma_buffer_offset,
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curr_pos, size);
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if (ctx->cl_dev.curr_spib_pos == ctx->cl_dev.bufsize)
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ctx->cl_dev.dma_buffer_offset = 0;
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else
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ctx->cl_dev.dma_buffer_offset = ctx->cl_dev.curr_spib_pos;
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ctx->cl_dev.wait_condition = false;
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if (intr_enable)
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skl_cldma_int_enable(ctx);
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ctx->cl_dev.ops.cl_setup_spb(ctx, ctx->cl_dev.curr_spib_pos, trigger);
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if (trigger)
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ctx->cl_dev.ops.cl_trigger(ctx, true);
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}
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/*
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* The CL dma doesn't have any way to update the transfer status until a BDL
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* buffer is fully transferred
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*
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* So Copying is divided in two parts.
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* 1. Interrupt on buffer done where the size to be transferred is more than
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* ring buffer size.
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* 2. Polling on fw register to identify if data left to transferred doesn't
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* fill the ring buffer. Caller takes care of polling the required status
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* register to identify the transfer status.
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* 3. if wait flag is set, waits for DBL interrupt to copy the next chunk till
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* bytes_left is 0.
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* if wait flag is not set, doesn't wait for BDL interrupt. after ccopying
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* the first chunk return the no of bytes_left to be copied.
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*/
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static int
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skl_cldma_copy_to_buf(struct sst_dsp *ctx, const void *bin,
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u32 total_size, bool wait)
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{
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int ret;
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bool start = true;
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unsigned int excess_bytes;
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u32 size;
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unsigned int bytes_left = total_size;
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const void *curr_pos = bin;
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if (total_size <= 0)
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return -EINVAL;
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dev_dbg(ctx->dev, "%s: Total binary size: %u\n", __func__, bytes_left);
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while (bytes_left) {
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if (bytes_left > ctx->cl_dev.bufsize) {
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/*
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* dma transfers only till the write pointer as
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* updated in spib
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*/
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if (ctx->cl_dev.curr_spib_pos == 0)
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ctx->cl_dev.curr_spib_pos = ctx->cl_dev.bufsize;
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size = ctx->cl_dev.bufsize;
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skl_cldma_fill_buffer(ctx, size, curr_pos, true, start);
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if (wait) {
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start = false;
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ret = skl_cldma_wait_interruptible(ctx);
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if (ret < 0) {
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skl_cldma_stop(ctx);
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return ret;
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}
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}
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} else {
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skl_cldma_int_disable(ctx);
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if ((ctx->cl_dev.curr_spib_pos + bytes_left)
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<= ctx->cl_dev.bufsize) {
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ctx->cl_dev.curr_spib_pos += bytes_left;
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} else {
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excess_bytes = bytes_left -
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(ctx->cl_dev.bufsize -
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ctx->cl_dev.curr_spib_pos);
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ctx->cl_dev.curr_spib_pos = excess_bytes;
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}
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size = bytes_left;
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skl_cldma_fill_buffer(ctx, size,
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curr_pos, false, start);
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}
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bytes_left -= size;
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curr_pos = curr_pos + size;
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if (!wait)
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return bytes_left;
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}
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return bytes_left;
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}
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void skl_cldma_process_intr(struct sst_dsp *ctx)
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{
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u8 cl_dma_intr_status;
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cl_dma_intr_status =
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sst_dsp_shim_read_unlocked(ctx, SKL_ADSP_REG_CL_SD_STS);
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if (!(cl_dma_intr_status & SKL_CL_DMA_SD_INT_COMPLETE))
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ctx->cl_dev.wake_status = SKL_CL_DMA_ERR;
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else
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ctx->cl_dev.wake_status = SKL_CL_DMA_BUF_COMPLETE;
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ctx->cl_dev.wait_condition = true;
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wake_up(&ctx->cl_dev.wait_queue);
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}
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int skl_cldma_prepare(struct sst_dsp *ctx)
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{
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int ret;
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__le32 *bdl;
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ctx->cl_dev.bufsize = SKL_MAX_BUFFER_SIZE;
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/* Allocate cl ops */
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ctx->cl_dev.ops.cl_setup_bdle = skl_cldma_setup_bdle;
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ctx->cl_dev.ops.cl_setup_controller = skl_cldma_setup_controller;
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ctx->cl_dev.ops.cl_setup_spb = skl_cldma_setup_spb;
|
||
|
|
ctx->cl_dev.ops.cl_cleanup_spb = skl_cldma_cleanup_spb;
|
||
|
|
ctx->cl_dev.ops.cl_trigger = skl_cldma_stream_run;
|
||
|
|
ctx->cl_dev.ops.cl_cleanup_controller = skl_cldma_cleanup;
|
||
|
|
ctx->cl_dev.ops.cl_copy_to_dmabuf = skl_cldma_copy_to_buf;
|
||
|
|
ctx->cl_dev.ops.cl_stop_dma = skl_cldma_stop;
|
||
|
|
|
||
|
|
/* Allocate buffer*/
|
||
|
|
ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
|
||
|
|
&ctx->cl_dev.dmab_data, ctx->cl_dev.bufsize);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(ctx->dev, "Alloc buffer for base fw failed: %x\n", ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
/* Setup Code loader BDL */
|
||
|
|
ret = ctx->dsp_ops.alloc_dma_buf(ctx->dev,
|
||
|
|
&ctx->cl_dev.dmab_bdl, PAGE_SIZE);
|
||
|
|
if (ret < 0) {
|
||
|
|
dev_err(ctx->dev, "Alloc buffer for blde failed: %x\n", ret);
|
||
|
|
ctx->dsp_ops.free_dma_buf(ctx->dev, &ctx->cl_dev.dmab_data);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
bdl = (__le32 *)ctx->cl_dev.dmab_bdl.area;
|
||
|
|
|
||
|
|
/* Allocate BDLs */
|
||
|
|
ctx->cl_dev.ops.cl_setup_bdle(ctx, &ctx->cl_dev.dmab_data,
|
||
|
|
&bdl, ctx->cl_dev.bufsize, 1);
|
||
|
|
ctx->cl_dev.ops.cl_setup_controller(ctx, &ctx->cl_dev.dmab_bdl,
|
||
|
|
ctx->cl_dev.bufsize, ctx->cl_dev.frags);
|
||
|
|
|
||
|
|
ctx->cl_dev.curr_spib_pos = 0;
|
||
|
|
ctx->cl_dev.dma_buffer_offset = 0;
|
||
|
|
init_waitqueue_head(&ctx->cl_dev.wait_queue);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|