95 lines
3.1 KiB
C
95 lines
3.1 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2021, Linaro Limited
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/clk-provider.h>
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#include <linux/module.h>
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#include <linux/device.h>
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#include <linux/platform_device.h>
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#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
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#include "q6dsp-lpass-clocks.h"
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#include "q6prm.h"
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#define Q6PRM_CLK(id) { \
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.clk_id = id, \
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.q6dsp_clk_id = Q6PRM_##id, \
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.name = #id, \
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.rate = 19200000, \
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}
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static const struct q6dsp_clk_init q6prm_clks[] = {
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Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_PRI_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SEC_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_TER_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_QUAD_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SPEAKER_I2S_OSR),
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Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_SEN_MI2S_EBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT0_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT1_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT2_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT3_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT4_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT5_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_INT6_MI2S_IBIT),
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Q6PRM_CLK(LPASS_CLK_ID_QUI_MI2S_OSR),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_NPL_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_TX_CORE_NPL_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_NPL_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_VA_CORE_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_WSA2_CORE_TX_2X_MCLK),
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Q6PRM_CLK(LPASS_CLK_ID_RX_CORE_MCLK2_2X_MCLK),
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Q6DSP_VOTE_CLK(LPASS_HW_MACRO_VOTE, Q6PRM_HW_CORE_ID_LPASS,
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"LPASS_HW_MACRO"),
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Q6DSP_VOTE_CLK(LPASS_HW_DCODEC_VOTE, Q6PRM_HW_CORE_ID_DCODEC,
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"LPASS_HW_DCODEC"),
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};
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static const struct q6dsp_clk_desc q6dsp_clk_q6prm __maybe_unused = {
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.clks = q6prm_clks,
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.num_clks = ARRAY_SIZE(q6prm_clks),
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.lpass_set_clk = q6prm_set_lpass_clock,
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.lpass_vote_clk = q6prm_vote_lpass_core_hw,
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.lpass_unvote_clk = q6prm_unvote_lpass_core_hw,
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};
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#ifdef CONFIG_OF
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static const struct of_device_id q6prm_clock_device_id[] = {
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{ .compatible = "qcom,q6prm-lpass-clocks", .data = &q6dsp_clk_q6prm },
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{},
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};
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MODULE_DEVICE_TABLE(of, q6prm_clock_device_id);
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#endif
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static struct platform_driver q6prm_clock_platform_driver = {
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.driver = {
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.name = "q6prm-lpass-clock",
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.of_match_table = of_match_ptr(q6prm_clock_device_id),
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},
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.probe = q6dsp_clock_dev_probe,
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};
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module_platform_driver(q6prm_clock_platform_driver);
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MODULE_DESCRIPTION("Q6 Proxy Resource Manager LPASS clock driver");
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MODULE_LICENSE("GPL");
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