206 lines
6.0 KiB
C
206 lines
6.0 KiB
C
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* tegra20_das.c - Tegra20 DAS driver
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*
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* Author: Stephen Warren <swarren@nvidia.com>
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* Copyright (C) 2010 - NVIDIA, Inc.
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*/
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <linux/slab.h>
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#include <sound/soc.h>
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#define DRV_NAME "tegra20-das"
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/* Register TEGRA20_DAS_DAP_CTRL_SEL */
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#define TEGRA20_DAS_DAP_CTRL_SEL 0x00
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#define TEGRA20_DAS_DAP_CTRL_SEL_COUNT 5
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#define TEGRA20_DAS_DAP_CTRL_SEL_STRIDE 4
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_P 31
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_MS_SEL_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_P 30
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA1_TX_RX_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_P 29
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_SDATA2_TX_RX_S 1
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P 0
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#define TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_S 5
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/* Values for field TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL */
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#define TEGRA20_DAS_DAP_SEL_DAC1 0
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#define TEGRA20_DAS_DAP_SEL_DAC2 1
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#define TEGRA20_DAS_DAP_SEL_DAC3 2
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#define TEGRA20_DAS_DAP_SEL_DAP1 16
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#define TEGRA20_DAS_DAP_SEL_DAP2 17
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#define TEGRA20_DAS_DAP_SEL_DAP3 18
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#define TEGRA20_DAS_DAP_SEL_DAP4 19
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#define TEGRA20_DAS_DAP_SEL_DAP5 20
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/* Register TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL */
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL 0x40
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_COUNT 3
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P 28
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_S 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P 24
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_S 4
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P 0
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#define TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_S 4
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/*
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* Values for:
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL
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* TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL
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*/
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#define TEGRA20_DAS_DAC_SEL_DAP1 0
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#define TEGRA20_DAS_DAC_SEL_DAP2 1
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#define TEGRA20_DAS_DAC_SEL_DAP3 2
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#define TEGRA20_DAS_DAC_SEL_DAP4 3
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#define TEGRA20_DAS_DAC_SEL_DAP5 4
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/*
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* Names/IDs of the DACs/DAPs.
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*/
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#define TEGRA20_DAS_DAP_ID_1 0
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#define TEGRA20_DAS_DAP_ID_2 1
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#define TEGRA20_DAS_DAP_ID_3 2
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#define TEGRA20_DAS_DAP_ID_4 3
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#define TEGRA20_DAS_DAP_ID_5 4
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#define TEGRA20_DAS_DAC_ID_1 0
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#define TEGRA20_DAS_DAC_ID_2 1
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#define TEGRA20_DAS_DAC_ID_3 2
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struct tegra20_das {
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struct regmap *regmap;
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};
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/*
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* Terminology:
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* DAS: Digital audio switch (HW module controlled by this driver)
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* DAP: Digital audio port (port/pins on Tegra device)
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* DAC: Digital audio controller (e.g. I2S or AC97 controller elsewhere)
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*
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* The Tegra DAS is a mux/cross-bar which can connect each DAP to a specific
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* DAC, or another DAP. When DAPs are connected, one must be the master and
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* one the slave. Each DAC allows selection of a specific DAP for input, to
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* cater for the case where N DAPs are connected to 1 DAC for broadcast
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* output.
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*
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* This driver is dumb; no attempt is made to ensure that a valid routing
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* configuration is programmed.
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*/
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static inline void tegra20_das_write(struct tegra20_das *das, u32 reg, u32 val)
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{
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regmap_write(das->regmap, reg, val);
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}
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static void tegra20_das_connect_dap_to_dac(struct tegra20_das *das, int dap, int dac)
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{
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u32 addr;
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u32 reg;
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addr = TEGRA20_DAS_DAP_CTRL_SEL +
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(dap * TEGRA20_DAS_DAP_CTRL_SEL_STRIDE);
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reg = dac << TEGRA20_DAS_DAP_CTRL_SEL_DAP_CTRL_SEL_P;
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tegra20_das_write(das, addr, reg);
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}
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static void tegra20_das_connect_dac_to_dap(struct tegra20_das *das, int dac, int dap)
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{
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u32 addr;
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u32 reg;
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addr = TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL +
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(dac * TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_STRIDE);
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reg = dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_CLK_SEL_P |
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dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA1_SEL_P |
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dap << TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL_DAC_SDATA2_SEL_P;
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tegra20_das_write(das, addr, reg);
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}
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#define LAST_REG(name) \
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(TEGRA20_DAS_##name + \
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(TEGRA20_DAS_##name##_STRIDE * (TEGRA20_DAS_##name##_COUNT - 1)))
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static bool tegra20_das_wr_rd_reg(struct device *dev, unsigned int reg)
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{
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if (reg <= LAST_REG(DAP_CTRL_SEL))
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return true;
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if ((reg >= TEGRA20_DAS_DAC_INPUT_DATA_CLK_SEL) &&
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(reg <= LAST_REG(DAC_INPUT_DATA_CLK_SEL)))
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return true;
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return false;
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}
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static const struct regmap_config tegra20_das_regmap_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = LAST_REG(DAC_INPUT_DATA_CLK_SEL),
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.writeable_reg = tegra20_das_wr_rd_reg,
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.readable_reg = tegra20_das_wr_rd_reg,
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.cache_type = REGCACHE_FLAT,
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};
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static int tegra20_das_probe(struct platform_device *pdev)
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{
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void __iomem *regs;
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struct tegra20_das *das;
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das = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_das), GFP_KERNEL);
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if (!das)
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return -ENOMEM;
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regs = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(regs))
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return PTR_ERR(regs);
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das->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
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&tegra20_das_regmap_config);
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if (IS_ERR(das->regmap)) {
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dev_err(&pdev->dev, "regmap init failed\n");
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return PTR_ERR(das->regmap);
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}
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tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_1,
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TEGRA20_DAS_DAP_SEL_DAC1);
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tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_1,
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TEGRA20_DAS_DAC_SEL_DAP1);
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tegra20_das_connect_dap_to_dac(das, TEGRA20_DAS_DAP_ID_3,
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TEGRA20_DAS_DAP_SEL_DAC3);
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tegra20_das_connect_dac_to_dap(das, TEGRA20_DAS_DAC_ID_3,
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TEGRA20_DAS_DAC_SEL_DAP3);
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return 0;
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}
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static const struct of_device_id tegra20_das_of_match[] = {
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{ .compatible = "nvidia,tegra20-das", },
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{},
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};
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static struct platform_driver tegra20_das_driver = {
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.probe = tegra20_das_probe,
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.driver = {
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.name = DRV_NAME,
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.of_match_table = tegra20_das_of_match,
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},
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};
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module_platform_driver(tegra20_das_driver);
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MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>");
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MODULE_DESCRIPTION("Tegra20 DAS driver");
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MODULE_LICENSE("GPL");
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MODULE_ALIAS("platform:" DRV_NAME);
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MODULE_DEVICE_TABLE(of, tegra20_das_of_match);
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