81 lines
2.3 KiB
YAML
81 lines
2.3 KiB
YAML
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: mediatek display DSC controller
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maintainers:
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- Chun-Kuang Hu <chunkuang.hu@kernel.org>
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- Philipp Zabel <p.zabel@pengutronix.de>
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description: |
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The DSC standard is a specification of the algorithms used for
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compressing and decompressing image display streams, including
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the specification of the syntax and semantics of the compressed
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video bit stream. DSC is designed for real-time systems with
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real-time compression, transmission, decompression and Display.
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properties:
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compatible:
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oneOf:
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- items:
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- const: mediatek,mt8195-disp-dsc
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: DSC Wrapper Clock
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power-domains:
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description: A phandle and PM domain specifier as defined by bindings of
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the power controller specified by phandle. See
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Documentation/devicetree/bindings/power/power-domain.yaml for details.
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mediatek,gce-client-reg:
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description:
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The register of client driver can be configured by gce with 4 arguments
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defined in this property, such as phandle of gce, subsys id,
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register offset and size.
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Each subsys id is mapping to a base address of display function blocks
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register which is defined in the gce header
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include/dt-bindings/gce/<chip>-gce.h.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- power-domains
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- clocks
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8195-clk.h>
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#include <dt-bindings/power/mt8195-power.h>
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#include <dt-bindings/gce/mt8195-gce.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dsc0: disp_dsc_wrap@1c009000 {
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compatible = "mediatek,mt8195-disp-dsc";
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reg = <0 0x1c009000 0 0x1000>;
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interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
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power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
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clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
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mediatek,gce-client-reg = <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
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};
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};
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