103 lines
2.5 KiB
YAML
103 lines
2.5 KiB
YAML
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# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/samsung,usb2-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung S5P/Exynos SoC USB 2.0 PHY
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maintainers:
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- Krzysztof Kozlowski <krzk@kernel.org>
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- Marek Szyprowski <m.szyprowski@samsung.com>
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- Sylwester Nawrocki <s.nawrocki@samsung.com>
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description: |
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The first phandle argument in the PHY specifier identifies the PHY, its
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meaning is compatible dependent. For the currently supported SoCs (Exynos4210
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and Exynos4212) it is as follows::
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0 - USB device ("device"),
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1 - USB host ("host"),
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2 - HSIC0 ("hsic0"),
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3 - HSIC1 ("hsic1"),
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Exynos3250 has only USB device phy available as phy 0.
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Exynos4210 and Exynos4212 use mode switching and require that mode switch
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register is supplied.
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properties:
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compatible:
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enum:
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- samsung,exynos3250-usb2-phy
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- samsung,exynos4210-usb2-phy
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- samsung,exynos4x12-usb2-phy
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- samsung,exynos5250-usb2-phy
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- samsung,exynos5420-usb2-phy
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- samsung,s5pv210-usb2-phy
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clocks:
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items:
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- description: PHY module gate clock.
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- description: Reference rate clock of PHY module.
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clock-names:
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items:
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- const: phy
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- const: ref
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"#phy-cells":
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const: 1
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reg:
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maxItems: 1
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samsung,pmureg-phandle:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to PMU system controller interface.
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samsung,sysreg-phandle:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to system registers interface.
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vbus-supply:
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description:
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VBUS power source.
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required:
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- compatible
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- clocks
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- clock-names
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- "#phy-cells"
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- reg
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- samsung,pmureg-phandle
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allOf:
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- if:
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properties:
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compatible:
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contains:
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enum:
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- samsung,exynos4x12-usb2-phy
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- samsung,exynos5250-usb2-phy
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- samsung,exynos5420-usb2-phy
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then:
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required:
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- samsung,sysreg-phandle
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5420.h>
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phy@12130000 {
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compatible = "samsung,exynos5420-usb2-phy";
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reg = <0x12130000 0x100>;
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#phy-cells = <1>;
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clocks = <&clock CLK_USBH20>, <&clock CLK_SCLK_USBPHY300>;
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clock-names = "phy", "ref";
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samsung,sysreg-phandle = <&sysreg_system_controller>;
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samsung,pmureg-phandle = <&pmu_system_controller>;
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};
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