146 lines
4.9 KiB
C
146 lines
4.9 KiB
C
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* PDM Microphone Interface for the NXP i.MX SoC
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* Copyright 2018 NXP
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*/
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#ifndef _FSL_MICFIL_H
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#define _FSL_MICFIL_H
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/* MICFIL Register Map */
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#define REG_MICFIL_CTRL1 0x00
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#define REG_MICFIL_CTRL2 0x04
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#define REG_MICFIL_STAT 0x08
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#define REG_MICFIL_FIFO_CTRL 0x10
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#define REG_MICFIL_FIFO_STAT 0x14
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#define REG_MICFIL_DATACH0 0x24
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#define REG_MICFIL_DATACH1 0x28
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#define REG_MICFIL_DATACH2 0x2C
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#define REG_MICFIL_DATACH3 0x30
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#define REG_MICFIL_DATACH4 0x34
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#define REG_MICFIL_DATACH5 0x38
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#define REG_MICFIL_DATACH6 0x3C
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#define REG_MICFIL_DATACH7 0x40
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#define REG_MICFIL_DC_CTRL 0x64
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#define REG_MICFIL_OUT_CTRL 0x74
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#define REG_MICFIL_OUT_STAT 0x7C
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#define REG_MICFIL_VAD0_CTRL1 0x90
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#define REG_MICFIL_VAD0_CTRL2 0x94
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#define REG_MICFIL_VAD0_STAT 0x98
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#define REG_MICFIL_VAD0_SCONFIG 0x9C
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#define REG_MICFIL_VAD0_NCONFIG 0xA0
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#define REG_MICFIL_VAD0_NDATA 0xA4
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#define REG_MICFIL_VAD0_ZCD 0xA8
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/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
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#define MICFIL_CTRL1_MDIS BIT(31)
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#define MICFIL_CTRL1_DOZEN BIT(30)
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#define MICFIL_CTRL1_PDMIEN BIT(29)
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#define MICFIL_CTRL1_DBG BIT(28)
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#define MICFIL_CTRL1_SRES BIT(27)
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#define MICFIL_CTRL1_DBGE BIT(26)
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#define MICFIL_CTRL1_DISEL_DISABLE 0
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#define MICFIL_CTRL1_DISEL_DMA 1
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#define MICFIL_CTRL1_DISEL_IRQ 2
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#define MICFIL_CTRL1_DISEL GENMASK(25, 24)
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#define MICFIL_CTRL1_ERREN BIT(23)
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#define MICFIL_CTRL1_CHEN(ch) BIT(ch)
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/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
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#define MICFIL_CTRL2_QSEL_SHIFT 25
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#define MICFIL_CTRL2_QSEL GENMASK(27, 25)
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#define MICFIL_QSEL_MEDIUM_QUALITY 0
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#define MICFIL_QSEL_HIGH_QUALITY 1
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#define MICFIL_QSEL_LOW_QUALITY 7
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#define MICFIL_QSEL_VLOW0_QUALITY 6
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#define MICFIL_QSEL_VLOW1_QUALITY 5
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#define MICFIL_QSEL_VLOW2_QUALITY 4
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#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
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#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
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/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
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#define MICFIL_STAT_BSY_FIL BIT(31)
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#define MICFIL_STAT_FIR_RDY BIT(30)
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#define MICFIL_STAT_LOWFREQF BIT(29)
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#define MICFIL_STAT_CHXF(ch) BIT(ch)
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/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
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#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
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/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
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#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
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#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
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/* MICFIL DC Remover Control Register -- REG_MICFIL_DC_CTRL */
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#define MICFIL_DC_CTRL_CONFIG GENMASK(15, 0)
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#define MICFIL_DC_CHX_SHIFT(ch) ((ch) << 1)
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#define MICFIL_DC_CHX(ch) GENMASK((((ch) << 1) + 1), ((ch) << 1))
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#define MICFIL_DC_CUTOFF_21HZ 0
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#define MICFIL_DC_CUTOFF_83HZ 1
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#define MICFIL_DC_CUTOFF_152Hz 2
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#define MICFIL_DC_BYPASS 3
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/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
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#define MICFIL_VAD0_CTRL1_CHSEL GENMASK(26, 24)
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#define MICFIL_VAD0_CTRL1_CICOSR GENMASK(19, 16)
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#define MICFIL_VAD0_CTRL1_INITT GENMASK(12, 8)
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#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
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#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
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#define MICFIL_VAD0_CTRL1_IE BIT(2)
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#define MICFIL_VAD0_CTRL1_RST BIT(1)
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#define MICFIL_VAD0_CTRL1_EN BIT(0)
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/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
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#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
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#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
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#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
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#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
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#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
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#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
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/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
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#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
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#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
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#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
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/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
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#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
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#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
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#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
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#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
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#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
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#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
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/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
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#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
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#define MICFIL_VAD0_ZCD_ZCDADJ GENMASK(11, 8)
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#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
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#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
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#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
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/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
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#define MICFIL_VAD0_STAT_INITF BIT(31)
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#define MICFIL_VAD0_STAT_INSATF BIT(16)
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#define MICFIL_VAD0_STAT_EF BIT(15)
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#define MICFIL_VAD0_STAT_IF BIT(0)
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/* MICFIL Output Control Register */
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#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
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/* Constants */
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#define MICFIL_OUTPUT_CHANNELS 8
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#define MICFIL_FIFO_NUM 8
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#define FIFO_PTRWID 3
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#define FIFO_LEN BIT(FIFO_PTRWID)
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#define MICFIL_IRQ_LINES 2
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#define MICFIL_MAX_RETRY 25
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#define MICFIL_SLEEP_MIN 90000 /* in us */
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#define MICFIL_SLEEP_MAX 100000 /* in us */
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#define MICFIL_DMA_MAXBURST_RX 6
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#endif /* _FSL_MICFIL_H */
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