45 lines
1.8 KiB
ReStructuredText
45 lines
1.8 KiB
ReStructuredText
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Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE)
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=============================================================
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The ThunderX2 SoC PMU consists of independent, system-wide, per-socket
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PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
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Cavium Coherent Processor Interconnect (CCPI2).
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The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
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Events are counted for the default channel (i.e. channel 0) and prorated
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to the total number of channels/tiles.
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The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
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counters. Counters are independently programmable to different events and
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can be started and stopped individually. None of the counters support an
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overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
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The CCPI2 counters are 64-bit and assumed not to overflow in normal operation.
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PMU UNCORE (perf) driver:
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The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and
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L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
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(CCPI2) events simultaneously. The PMUs provide a description of their
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available events and configuration options under sysfs, see
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/sys/devices/uncore_<l3c_S/dmc_S/ccpi2_S/>; S is the socket id.
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The driver does not support sampling, therefore "perf record" will not
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work. Per-task perf sessions are also not supported.
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Examples::
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# perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1
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# perf stat -a -e \
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uncore_dmc_0/cnt_cycles/,\
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uncore_dmc_0/data_transfers/,\
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uncore_dmc_0/read_txns/,\
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uncore_dmc_0/write_txns/ sleep 1
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# perf stat -a -e \
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uncore_l3c_0/read_request/,\
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uncore_l3c_0/read_hit/,\
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uncore_l3c_0/inv_request/,\
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uncore_l3c_0/inv_hit/ sleep 1
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