116 lines
3.5 KiB
Plaintext
116 lines
3.5 KiB
Plaintext
NVIDIA Tegra Graphics Processing Units
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Required properties:
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- compatible: "nvidia,<gpu>"
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Currently recognized values:
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- nvidia,gk20a
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- nvidia,gm20b
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- nvidia,gp10b
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- nvidia,gv11b
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- reg: Physical base address and length of the controller's registers.
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Must contain two entries:
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- first entry for bar0
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- second entry for bar1
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- interrupts: Must contain an entry for each entry in interrupt-names.
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See ../interrupt-controller/interrupts.txt for details.
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- interrupt-names: Must include the following entries:
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- stall
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- nonstall
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- vdd-supply: regulator for supply voltage. Only required for GPUs not using
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power domains.
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- clocks: Must contain an entry for each entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must include the following entries:
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- gpu
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- pwr
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If the compatible string is "nvidia,gm20b", then the following clock
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is also required:
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- ref
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If the compatible string is "nvidia,gv11b", then the following clock is also
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required:
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- fuse
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- resets: Must contain an entry for each entry in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include the following entries:
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- gpu
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- power-domains: GPUs that make use of power domains can define this property
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instead of vdd-supply. Currently "nvidia,gp10b" makes use of this.
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Optional properties:
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- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details.
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Example for GK20A:
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gpu@57000000 {
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compatible = "nvidia,gk20a";
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reg = <0x0 0x57000000 0x0 0x01000000>,
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<0x0 0x58000000 0x0 0x01000000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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vdd-supply = <&vdd_gpu>;
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clocks = <&tegra_car TEGRA124_CLK_GPU>,
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<&tegra_car TEGRA124_CLK_PLL_P_OUT5>;
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clock-names = "gpu", "pwr";
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resets = <&tegra_car 184>;
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reset-names = "gpu";
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iommus = <&mc TEGRA_SWGROUP_GPU>;
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};
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Example for GM20B:
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gpu@57000000 {
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compatible = "nvidia,gm20b";
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reg = <0x0 0x57000000 0x0 0x01000000>,
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<0x0 0x58000000 0x0 0x01000000>;
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interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&tegra_car TEGRA210_CLK_GPU>,
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<&tegra_car TEGRA210_CLK_PLL_P_OUT5>,
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<&tegra_car TEGRA210_CLK_PLL_G_REF>;
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clock-names = "gpu", "pwr", "ref";
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resets = <&tegra_car 184>;
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reset-names = "gpu";
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iommus = <&mc TEGRA_SWGROUP_GPU>;
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};
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Example for GP10B:
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gpu@17000000 {
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compatible = "nvidia,gp10b";
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reg = <0x0 0x17000000 0x0 0x1000000>,
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<0x0 0x18000000 0x0 0x1000000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH
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GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&bpmp TEGRA186_CLK_GPCCLK>,
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<&bpmp TEGRA186_CLK_GPU>;
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clock-names = "gpu", "pwr";
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resets = <&bpmp TEGRA186_RESET_GPU>;
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reset-names = "gpu";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>;
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iommus = <&smmu TEGRA186_SID_GPU>;
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};
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Example for GV11B:
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gpu@17000000 {
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compatible = "nvidia,gv11b";
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reg = <0x17000000 0x1000000>,
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<0x18000000 0x1000000>;
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interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "stall", "nonstall";
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clocks = <&bpmp TEGRA194_CLK_GPCCLK>,
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<&bpmp TEGRA194_CLK_GPU_PWR>,
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<&bpmp TEGRA194_CLK_FUSE>;
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clock-names = "gpu", "pwr", "fuse";
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resets = <&bpmp TEGRA194_RESET_GPU>;
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reset-names = "gpu";
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dma-coherent;
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power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>;
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iommus = <&smmu TEGRA194_SID_GPU>;
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};
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