92 lines
2.7 KiB
YAML
92 lines
2.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Broadcom BCM7038-style Level 1 interrupt controller
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description: >
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This block is a first level interrupt controller that is typically connected
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directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
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since BCM7038 has contained this hardware.
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Key elements of the hardware design include:
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- 64, 96, 128, or 160 incoming level IRQ lines
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- Most onchip peripherals are wired directly to an L1 input
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- A separate instance of the register set for each CPU, allowing individual
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peripheral IRQs to be routed to any CPU
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- Atomic mask/unmask operations
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- No polarity/level/edge settings
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- No FIFO or priority encoder logic; software is expected to read all
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2-5 status words to determine which IRQs are pending
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If multiple reg ranges and interrupt-parent entries are present on an SMP
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system, the driver will allow IRQ SMP affinity to be set up through the
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/proc/irq/ interface. In the simplest possible configuration, only one
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reg range and one interrupt-parent is needed.
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maintainers:
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- Florian Fainelli <f.fainelli@gmail.com>
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allOf:
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- $ref: /schemas/interrupt-controller.yaml#
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properties:
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compatible:
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const: brcm,bcm7038-l1-intc
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reg:
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description: >
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Specifies the base physical address and size of the registers
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the number of supported IRQs is inferred from the size argument
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interrupt-controller: true
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"#interrupt-cells":
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const: 1
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interrupts:
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description: >
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Specifies the interrupt line(s) in the interrupt-parent controller node;
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valid values depend on the type of parent interrupt controller
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brcm,irq-can-wake:
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type: boolean
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description: >
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If present, this means the L1 controller can be used as a
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wakeup source for system suspend/resume.
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brcm,int-fwd-mask:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description:
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If present, a bit mask to indicate which interrupts have already been
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configured by the firmware and should be left unmanaged. This should
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have one 32-bit word per status/set/clear/mask group.
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required:
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- compatible
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- reg
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- interrupt-controller
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- "#interrupt-cells"
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- interrupts
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additionalProperties: false
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examples:
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- |
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periph_intc: interrupt-controller@1041a400 {
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compatible = "brcm,bcm7038-l1-intc";
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reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpu_intc>;
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interrupts = <2>, <3>;
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};
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