yannick.naumann/RT-Task-Generator-QEMU
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  • e3867bad0d tcg/ppc: Introduce HostAddress Richard Henderson 2023-04-23 20:10:00 +01:00
  • 6073988eef tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-06 12:53:46 -07:00
  • eb664d0c52 tcg/mips: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-06 12:52:26 -07:00
  • 9a2027b7a2 tcg/loongarch64: Introduce HostAddress Richard Henderson 2023-04-23 16:31:16 +01:00
  • 7f67e58236 tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-08 15:13:04 -07:00
  • 1df6d611bd tcg/arm: Introduce HostAddress Richard Henderson 2023-04-22 05:32:22 +01:00
  • 737fb471ed tcg/arm: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-06 12:51:01 -07:00
  • 7f65be51b6 tcg/aarch64: Introduce HostAddress Richard Henderson 2023-04-21 09:52:25 +01:00
  • ff0cc85ef3 tcg/aarch64: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-06 12:47:15 -07:00
  • a48f1c7415 tcg/i386: Introduce tcg_out_testi Richard Henderson 2022-11-08 14:30:27 +11:00
  • 3c2c35e23e tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load Richard Henderson 2023-04-19 18:43:35 +02:00
  • 61713c29a9 tcg/i386: Introduce HostAddress Richard Henderson 2023-04-19 18:29:14 +02:00
  • 3174941fe0 tcg/i386: Generalize multi-part load overlap test Richard Henderson 2023-04-16 15:56:41 +02:00
  • bf12e2240d tcg/i386: Rationalize args to tcg_out_qemu_{ld,st} Richard Henderson 2023-04-06 12:42:40 -07:00
  • 3ed8d2d4c8 target/sparc: Remove TARGET_ALIGNED_ONLY Richard Henderson 2023-05-02 16:15:23 +01:00
  • 60abd45224 target/sparc: Use cpu_ld*_code_mmu Richard Henderson 2023-05-02 16:14:19 +01:00
  • 316b6783f1 target/sparc: Use MO_ALIGN where required Richard Henderson 2023-05-02 16:12:44 +01:00
  • 0bd447ee64 target/hppa: Remove TARGET_ALIGNED_ONLY Richard Henderson 2023-05-02 09:53:13 +01:00
  • 2d4afb03e4 target/hppa: Use MO_ALIGN for system UNALIGN() Richard Henderson 2023-05-02 15:30:10 +01:00
  • e10e98bdb0 target/alpha: Remove TARGET_ALIGNED_ONLY Richard Henderson 2023-05-02 09:43:44 +01:00
  • 33948b68a7 target/alpha: Use MO_ALIGN where required Richard Henderson 2023-05-02 15:36:47 +01:00
  • 6ffaac9ca0 target/alpha: Use MO_ALIGN for system UNALIGN() Richard Henderson 2023-05-02 15:31:25 +01:00
  • 5fa7c0882d tcg: Remove compatability helpers for qemu ld/st Richard Henderson 2023-05-02 14:57:41 +01:00
  • f0aca2a912 target/xtensa: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson 2023-05-02 14:57:40 +01:00
  • 0814911883 target/sparc: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson 2023-05-02 14:57:39 +01:00
  • e87027d022 target/s390x: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson 2023-05-02 14:57:38 +01:00
  • 6d0cad1259 target/mips: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson 2023-05-02 14:57:37 +01:00
  • b7a94da955 target/m68k: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson 2023-05-02 14:57:36 +01:00
  • 53b26d253c target/Hexagon: Finish conversion to tcg_gen_qemu_{ld, st}_* Richard Henderson 2023-05-02 14:57:35 +01:00
  • a9a9c3fa6f target/cris: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson 2023-05-02 14:57:34 +01:00
  • 8b4506e5d2 target/avr: Finish conversion to tcg_gen_qemu_{ld,st}_* Richard Henderson 2023-05-02 14:57:33 +01:00
  • 1098cc3fcf softfloat: Fix the incorrect computation in float32_exp2 Shivaprasad G Bhat 2023-05-02 20:55:30 +05:30
  • b35261b1a6 hw/ppc/Kconfig: NVDIMM is a hard requirement for the pseries machine Thomas Huth 2023-05-04 20:05:21 +02:00
  • 0eb9fcc735 tests: tcg: ppc64: Add tests for Vector Extract Mask Instructions Shivaprasad G Bhat 2023-05-04 05:36:04 -04:00
  • 6a5d81b172 tcg: ppc64: Fix mask generation for vextractdm Shivaprasad G Bhat 2023-05-04 05:35:39 -04:00
  • fcdae0122d MAINTAINERS: Adding myself in the list for ppc/spapr Harsh Prateek Bora 2023-05-03 15:06:19 +05:30
  • 2060436aab ppc: spapr: cleanup cr get/set with helpers. Harsh Prateek Bora 2023-05-03 15:06:18 +05:30
  • 1b336bb63e hw/display/sm501: Remove unneeded increment from loop BALATON Zoltan 2023-04-05 17:57:19 +02:00
  • c2d3d1c294 audio/pwaudio.c: Add Pipewire audio backend for QEMU Dorinda Bassey 2023-04-17 12:56:54 +02:00
  • a9fe9e191b Merge tag 'pull-riscv-to-apply-20230505-1' of https://github.com/alistair23/qemu into staging Richard Henderson 2023-05-05 09:25:13 +01:00
  • e1d084a852 target/riscv: add Ventana's Veyron V1 CPU Rahul Pathak 2023-04-18 09:36:24 -03:00
  • 190e9f8ec1 riscv: Make sure an exception is raised if a pte is malformed Alexandre Ghiti 2023-04-20 17:02:20 +02:00
  • 7bf14a2f37 target/riscv: Fix Guest Physical Address Translation Irina Ryapolova 2023-04-18 10:54:23 +03:00
  • eae04c4c13 target/riscv: Restore the predicate() NULL check behavior Bin Meng 2023-04-17 12:30:54 +08:00
  • 9e1a30d342 target/riscv: add TYPE_RISCV_DYNAMIC_CPU Daniel Henrique Barboza 2023-04-11 15:35:11 -03:00
  • c0177f911f target/riscv: add query-cpy-definitions support Daniel Henrique Barboza 2023-04-11 15:35:10 -03:00
  • 85840bd2e0 target/riscv: add CPU QOM header Daniel Henrique Barboza 2023-04-11 15:35:09 -03:00
  • 2e6dba15cd hw/intc/riscv_aplic: Zero init APLIC internal state Ivan Klokov 2023-04-13 16:34:32 +03:00
  • 38303e8a2c target/riscv: Reorg sum check in get_physical_address Richard Henderson 2023-04-12 13:43:33 +02:00
  • e1dd15076b target/riscv: Reorg access check in get_physical_address Richard Henderson 2023-04-12 13:43:32 +02:00
  • a9d2e3ed4d target/riscv: Merge checks for reserved pte flags Richard Henderson 2023-04-12 13:43:31 +02:00
  • 356c8331d6 target/riscv: Don't modify SUM with is_debug Richard Henderson 2023-04-12 13:43:30 +02:00
  • 0a19bf5e37 target/riscv: Suppress pte update with is_debug Richard Henderson 2023-04-12 13:43:29 +02:00
  • 59688aa023 target/riscv: Move leaf pte processing out of level loop Richard Henderson 2023-04-12 13:43:28 +02:00
  • 8d6a00cdc0 target/riscv: Hoist pbmte and hade out of the level loop Richard Henderson 2023-04-12 13:43:27 +02:00
  • a427c83633 target/riscv: Hoist second stage mode change to callers Richard Henderson 2023-04-12 13:43:26 +02:00
  • eaecd473ca target/riscv: Check SUM in the correct register Richard Henderson 2023-04-12 13:43:25 +02:00
  • 696bacde95 target/riscv: Set MMU_2STAGE_BIT in riscv_cpu_mmu_index Richard Henderson 2023-04-12 13:43:24 +02:00
  • 9de7b7b5c7 target/riscv: Move hstatus.spvp check to check_access_hlsv Richard Henderson 2023-04-12 13:43:23 +02:00
  • 02369f7906 target/riscv: Introduce mmuidx_2stage Richard Henderson 2023-04-12 13:43:22 +02:00
  • 340b5805db target/riscv: Introduce mmuidx_priv Richard Henderson 2023-04-12 13:43:21 +02:00
  • 4005a799f1 target/riscv: Introduce mmuidx_sum Richard Henderson 2023-04-12 13:43:20 +02:00
  • 3df44173e9 target/riscv: Rename MMU_HYP_ACCESS_BIT to MMU_2STAGE_BIT Richard Henderson 2023-04-12 13:43:19 +02:00
  • 0f58cbbeea target/riscv: Handle HLV, HSV via helpers Richard Henderson 2023-04-12 13:43:18 +02:00
  • a7f112c5fd target/riscv: Use cpu_ld*_code_mmu for HLVX Richard Henderson 2023-04-12 13:43:17 +02:00
  • c8f8a9957e target/riscv: Reduce overhead of MSTATUS_SUM change Fei Wu 2023-04-12 13:43:15 +02:00
  • 47debc7280 target/riscv: Separate priv from mmu_idx Fei Wu 2023-04-12 13:43:14 +02:00
  • 4acaa133b1 target/riscv: Add a tb flags field for vstart LIU Zhiwei 2023-04-12 13:43:13 +02:00
  • 25f3ddff5f target/riscv: Remove mstatus_hs_{fs, vs} from tb_flags Richard Henderson 2023-04-12 13:43:12 +02:00
  • ebd476488d target/riscv: Encode the FS and VS on a normal way for tb flags LIU Zhiwei 2023-04-12 13:43:11 +02:00
  • 42967f4073 target/riscv: Add a general status enum for extensions LIU Zhiwei 2023-04-12 13:43:10 +02:00
  • f196639024 target/riscv: Extract virt enabled state from tb flags LIU Zhiwei 2023-04-12 13:43:09 +02:00
  • d6db7c975e target/riscv: fix H extension TVM trap Yi Chen 2023-04-06 18:15:59 +08:00
  • 9ba63f9442 target/riscv: Use check for relationship between Zdinx/Zhinx{min} and Zfinx Weiwei Li 2023-04-08 21:59:08 +08:00
  • 0c98ccef49 target/riscv: Legalize MPP value in write_mstatus Weiwei Li 2023-04-07 09:47:43 +08:00
  • 44b8f74b00 target/riscv: Use PRV_RESERVED instead of PRV_H Weiwei Li 2023-04-07 09:47:42 +08:00
  • 04803c3ddb target/riscv: Fix the mstatus.MPP value after executing MRET Weiwei Li 2023-04-07 09:47:41 +08:00
  • dd8f244f35 target/riscv/cpu.c: redesign register_cpu_props() Daniel Henrique Barboza 2023-04-06 15:03:51 -03:00
  • 4f13abcb2b target/riscv: add RVG and remove cpu->cfg.ext_g Daniel Henrique Barboza 2023-04-06 15:03:50 -03:00
  • 8ef67c6637 target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init() Daniel Henrique Barboza 2023-04-06 15:03:49 -03:00
  • 7295b18606 target/riscv: remove riscv_cpu_sync_misa_cfg() Daniel Henrique Barboza 2023-04-06 15:03:48 -03:00
  • 3e7674fd1a target/riscv: remove cpu->cfg.ext_v Daniel Henrique Barboza 2023-04-06 15:03:47 -03:00
  • 64f4b541c5 target/riscv: remove cpu->cfg.ext_j Daniel Henrique Barboza 2023-04-06 15:03:46 -03:00
  • b5c042e8a0 target/riscv: remove cpu->cfg.ext_h Daniel Henrique Barboza 2023-04-06 15:03:45 -03:00
  • e17801e170 target/riscv: remove cpu->cfg.ext_u Daniel Henrique Barboza 2023-04-06 15:03:44 -03:00
  • f1ea2a52dc target/riscv: remove cpu->cfg.ext_s Daniel Henrique Barboza 2023-04-06 15:03:43 -03:00
  • 1a36e23a62 target/riscv: remove cpu->cfg.ext_m Daniel Henrique Barboza 2023-04-06 15:03:42 -03:00
  • 427d8e7dd8 target/riscv: remove cpu->cfg.ext_e Daniel Henrique Barboza 2023-04-06 15:03:41 -03:00
  • 74828eabf2 target/riscv: remove cpu->cfg.ext_i Daniel Henrique Barboza 2023-04-06 15:03:40 -03:00
  • 4b33598fbe target/riscv: remove cpu->cfg.ext_f Daniel Henrique Barboza 2023-04-06 15:03:39 -03:00
  • ffffd954ba target/riscv: remove cpu->cfg.ext_d Daniel Henrique Barboza 2023-04-06 15:03:38 -03:00
  • c00226e1f0 target/riscv: remove cpu->cfg.ext_c Daniel Henrique Barboza 2023-04-06 15:03:37 -03:00
  • 4c759943ec target/riscv: remove cpu->cfg.ext_a Daniel Henrique Barboza 2023-04-06 15:03:36 -03:00
  • b3df64c89b target/riscv: introduce riscv_cpu_add_misa_properties() Daniel Henrique Barboza 2023-04-06 15:03:35 -03:00
  • ccc84a7588 target/riscv/cpu.c: remove 'multi_letter' from isa_ext_data Daniel Henrique Barboza 2023-04-06 15:03:34 -03:00
  • 6508272a8a target/riscv: remove MISA properties from isa_edata_arr[] Daniel Henrique Barboza 2023-04-06 15:03:33 -03:00
  • 1ffa805c9d target/riscv: sync env->misa_ext* with cpu->cfg in realize() Daniel Henrique Barboza 2023-04-06 15:03:32 -03:00
  • 66247edc8b hw/riscv: Add signature dump function for spike to run ACT tests Weiwei Li 2023-04-05 17:57:20 +08:00
  • 246f87960a target/riscv: Fix lines with over 80 characters Weiwei Li 2023-04-05 16:58:13 +08:00
  • 3b57254d8a target/riscv: Fix format for comments Weiwei Li 2023-04-05 16:58:12 +08:00