yannick.naumann/RT-Task-Generator-QEMU
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  • 167f487358 Revert "hw/i386: pass RNG seed via setup_data entry" Michael S. Tsirkin 2023-02-08 16:05:35 -05:00
  • ae80d81cfa Revert "x86: return modified setup_data only if read as memory, not as file" Michael S. Tsirkin 2023-02-08 16:04:40 -05:00
  • ea96a78477 Revert "x86: use typedef for SetupData struct" Michael S. Tsirkin 2023-02-08 15:55:41 -05:00
  • fdc27ced04 Revert "x86: reinitialize RNG seed on system reboot" Michael S. Tsirkin 2023-02-08 15:55:40 -05:00
  • b4bfa0a31d Revert "x86: re-initialize RNG seed when selecting kernel" Michael S. Tsirkin 2023-02-08 15:55:39 -05:00
  • ef82d893de Revert "x86: do not re-randomize RNG seed on snapshot load" Michael S. Tsirkin 2023-02-08 15:55:38 -05:00
  • b34f2fd17e Revert "x86: don't let decompressed kernel image clobber setup_data" Michael S. Tsirkin 2023-02-08 15:55:36 -05:00
  • 60d09b8dc7 hw/smbios: fix field corruption in type 4 table Julia Suvorova 2023-02-23 13:57:47 +01:00
  • 0f3fea2171 target/ppc: Restrict 'qapi-commands-machine.h' to system emulation Philippe Mathieu-Daudé 2023-02-23 16:55:40 +01:00
  • 381b43f855 target/loongarch: Restrict 'qapi-commands-machine.h' to system emulation Philippe Mathieu-Daudé 2023-02-23 16:55:39 +01:00
  • 390dbc6e2e target/i386: Restrict 'qapi-commands-machine.h' to system emulation Philippe Mathieu-Daudé 2023-02-23 16:55:38 +01:00
  • 3362f04dbc target/arm: Restrict 'qapi-commands-machine.h' to system emulation Philippe Mathieu-Daudé 2023-02-23 16:55:37 +01:00
  • 3715103298
         Merge patch series "target/riscv: some vector_helper.c cleanups" Palmer Dabbelt 2023-03-01 18:09:48 -08:00
  • 86247c51ff
         target/riscv/vector_helper.c: avoid env_archcpu() when reading RISCVCPUConfig Daniel Henrique Barboza 2023-02-26 14:05:14 -03:00
  • e130683ffb
         target/riscv/vector_helper.c: create vext_set_tail_elems_1s() Daniel Henrique Barboza 2023-02-26 14:05:13 -03:00
  • 0b28c7ea0e
         Merge patch series "RISCVCPUConfig related cleanups" Palmer Dabbelt 2023-03-01 17:42:46 -08:00
  • 01af27e398
         target/riscv/csr.c: avoid env_archcpu() usages when reading RISCVCPUConfig Daniel Henrique Barboza 2023-02-24 14:45:20 -03:00
  • a9a4e39fd2
         target/riscv/csr.c: use riscv_cpu_cfg() to avoid env_cpu() pointers Daniel Henrique Barboza 2023-02-24 14:45:19 -03:00
  • 96b1b00058
         target/riscv/csr.c: simplify mctr() Daniel Henrique Barboza 2023-02-24 14:45:18 -03:00
  • 3c7d54f945
         target/riscv/csr.c: use env_archcpu() in ctr() Daniel Henrique Barboza 2023-02-24 14:45:17 -03:00
  • 8e5aded3de
         Merge patch series "target/riscv: Add support for Svadu extension" Palmer Dabbelt 2023-03-01 17:28:21 -08:00
  • 62108f05e7
         target/riscv: Export Svadu property Weiwei Li 2023-02-24 12:08:52 +08:00
  • 0af3f115e6
         target/riscv: Add *envcfg.HADE related check in address translation Weiwei Li 2023-02-24 12:08:51 +08:00
  • 7a6613da99
         target/riscv: Add *envcfg.PBMTE related check in address translation Weiwei Li 2023-02-24 12:08:50 +08:00
  • 0d190bd394
         target/riscv: Add csr support for svadu Weiwei Li 2023-02-24 12:08:49 +08:00
  • 6f3eb1a3c8
         target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg Weiwei Li 2023-02-24 12:08:48 +08:00
  • 73ec0ead67
         target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions Weiwei Li 2023-02-24 12:08:47 +08:00
  • fc9ec3625f
         hw/riscv: Move the dtb load bits outside of create_fdt() Bin Meng 2023-02-28 15:45:22 +08:00
  • d43d54ca2b
         hw/riscv: Skip re-generating DT nodes for a given DTB Bin Meng 2023-02-28 15:45:21 +08:00
  • b8e1f32cda
         target/riscv: Add support for Zicond extension Weiwei Li 2023-02-21 17:10:09 +08:00
  • b7fa70e2af
         RISC-V: XTheadMemPair: Remove register restrictions for store-pair Christoph Müllner 2023-02-20 10:56:12 +01:00
  • ae9c326fb6
         target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages Shaobo Song 2023-02-20 07:27:32 +00:00
  • 73b9da4aa3
         Merge patch series "target/riscv: Various fixes to gdbstub and CSR access" Palmer Dabbelt 2023-03-01 16:40:30 -08:00
  • fb5bd4dcae
         target/riscv: Group all predicate() routines together Bin Meng 2023-02-28 21:45:35 +08:00
  • 9e83a35661
         target/riscv: Drop priv level check in mseccfg predicate() Bin Meng 2023-02-28 21:45:34 +08:00
  • e4e1f216a1
         target/riscv: Allow debugger to access sstc CSRs Bin Meng 2023-02-28 21:45:33 +08:00
  • 0308fc6219
         target/riscv: Allow debugger to access {h, s}stateen CSRs Bin Meng 2023-02-28 21:45:32 +08:00
  • ddb10742f1
         target/riscv: Allow debugger to access seed CSR Bin Meng 2023-02-28 21:45:31 +08:00
  • fb517fdb15
         target/riscv: Allow debugger to access user timer and counter CSRs Bin Meng 2023-02-28 21:45:30 +08:00
  • 7eac8f4191
         target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml Bin Meng 2023-02-28 21:45:29 +08:00
  • a1f0083c6e
         target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate() Bin Meng 2023-02-28 18:40:27 +08:00
  • 04733fb091
         target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64 Bin Meng 2023-02-28 18:40:26 +08:00
  • 94e297071b
         target/riscv: Simplify getting RISCVCPU pointer from env Bin Meng 2023-02-28 18:40:25 +08:00
  • 77ad639cb1
         target/riscv: Simplify {read, write}_pmpcfg() a little bit Bin Meng 2023-02-28 18:40:24 +08:00
  • a7e407b3f8
         target/riscv: Use 'bool' type for read_only Bin Meng 2023-02-28 18:40:23 +08:00
  • 8c7feddddd
         target/riscv: Coding style fixes in csr.c Bin Meng 2023-02-28 18:40:22 +08:00
  • e17e2c7cb9
         target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled Bin Meng 2023-02-28 18:40:21 +08:00
  • 28eb8bee83
         target/riscv: gdbstub: Minor change for better readability Bin Meng 2023-02-28 18:40:20 +08:00
  • 0ee342256a
         target/riscv: Use g_assert() for the predicate() NULL check Bin Meng 2023-02-28 18:40:19 +08:00
  • a5e0f68652
         target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check() Bin Meng 2023-02-28 18:40:18 +08:00
  • 0bc71ee0b7
         target/riscv: gdbstub: Check priv spec version before reporting CSR Bin Meng 2023-02-28 18:40:17 +08:00
  • 312f632f4c
         Merge patch series "target/riscv: Some updates to float point related extensions" Palmer Dabbelt 2023-03-01 14:13:28 -08:00
  • d3e6d5762b
         Merge patch series "make write_misa a no-op and FEATURE_* cleanups" Palmer Dabbelt 2023-03-01 13:47:18 -08:00
  • 058d9d302e
         target/riscv: Expose properties for Zv* extensions Weiwei Li 2023-02-15 10:05:39 +08:00
  • c1027460dc
         target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc Weiwei Li 2023-02-15 10:05:38 +08:00
  • 6ad831ebf1
         target/riscv: Fix check for vector load/store instructions when EEW=64 Weiwei Li 2023-02-15 10:05:37 +08:00
  • e80865e5f3
         target/riscv: Add support for Zvfh/zvfhmin extensions Weiwei Li 2023-02-15 10:05:36 +08:00
  • 2bc2853f15
         target/riscv: Remove redundunt check for zve32f and zve64f Weiwei Li 2023-02-15 10:05:35 +08:00
  • 732b902dd5
         target/riscv: Replace check for F/D to Zve32f/Zve64d in trans_rvv.c.inc Weiwei Li 2023-02-15 10:05:34 +08:00
  • 3f4a5a5314
         target/riscv: Simplify check for Zve32f and Zve64f Weiwei Li 2023-02-15 10:05:33 +08:00
  • 51f33081ef
         target/riscv: Indent fixes in cpu.c Weiwei Li 2023-02-15 10:05:32 +08:00
  • 2e60f9ec2c
         target/riscv: Add property check for Zvfh{min} extensions Weiwei Li 2023-02-15 10:05:31 +08:00
  • e7f0a803a7
         target/riscv: Fix relationship between V, Zve*, F and D Weiwei Li 2023-02-15 10:05:30 +08:00
  • a7336161f0
         target/riscv: Add cfg properties for Zv* extensions Weiwei Li 2023-02-15 10:05:29 +08:00
  • 94bdf6ee10
         target/riscv: Simplify the check for Zfhmin and Zhinxmin Weiwei Li 2023-02-15 10:05:28 +08:00
  • a0d805f035
         target/riscv: Fix the relationship between Zhinxmin and Zhinx Weiwei Li 2023-02-15 10:05:27 +08:00
  • 1d2cb5a868
         target/riscv: Fix the relationship between Zfhmin and Zfh Weiwei Li 2023-02-15 10:05:26 +08:00
  • 1e2de2b828
         target/riscv/cpu: remove CPUArchState::features and friends Daniel Henrique Barboza 2023-02-22 15:52:05 -03:00
  • dcf654a3e8
         target/riscv: remove RISCV_FEATURE_MMU Daniel Henrique Barboza 2023-02-22 15:52:04 -03:00
  • c95c9d200e
         hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus() Daniel Henrique Barboza 2023-02-22 15:52:03 -03:00
  • 3fe40ef5a9
         target/riscv: remove RISCV_FEATURE_PMP Daniel Henrique Barboza 2023-02-22 15:52:02 -03:00
  • 6a3ffda2ba
         target/riscv: remove RISCV_FEATURE_EPMP Daniel Henrique Barboza 2023-02-22 15:52:01 -03:00
  • 09631441e5
         target/riscv/cpu.c: error out if EPMP is enabled without PMP Daniel Henrique Barboza 2023-02-22 15:52:00 -03:00
  • cdfb290569
         target/riscv: remove RISCV_FEATURE_DEBUG Daniel Henrique Barboza 2023-02-22 15:51:59 -03:00
  • 54bd9b6ec3
         target/riscv: allow MISA writes as experimental Daniel Henrique Barboza 2023-02-22 15:51:58 -03:00
  • 5b17fefb90
         target/riscv: do not mask unsupported QEMU extensions in write_misa() Daniel Henrique Barboza 2023-02-22 15:51:57 -03:00
  • d4ea711704
         target/riscv: introduce riscv_cpu_cfg() Daniel Henrique Barboza 2023-02-22 15:51:56 -03:00
  • 76f5801a83 readline: fix hmp completion issue Dongli Zhang 2023-02-06 20:52:41 -08:00
  • a2b5f8b8ab Merge tag 'pull-tcg-20230301' of https://gitlab.com/rth7680/qemu into staging Peter Maydell 2023-03-01 19:19:20 +00:00
  • 6da777e212 bsd-user: implement sysctlbyname(2) Kyle Evans 2023-02-10 11:16:25 -07:00
  • 7adda6de6d bsd-user: do_freebsd_sysctl helper for sysctl(2) Kyle Evans 2023-02-10 10:02:45 -07:00
  • 248a485bf6 bsd-user: Start translation of arch-specific sysctls Juergen Lock 2023-02-10 15:24:45 -07:00
  • dd7a627ac7 bsd-user: common routine do_freebsd_sysctl_oid for all sysctl variants Juergen Lock 2023-02-10 15:24:45 -07:00
  • 0394968a44 bsd-user: sysctl helper funtions: sysctl_name2oid and sysctl_oidfmt Juergen Lock 2023-02-10 15:13:30 -07:00
  • efba70de54 bsd-user: Helper routines oidfmt Stacey Son 2023-02-10 10:17:29 -07:00
  • 0867507857 bsd-user: various helper routines for sysctl Warner Losh 2023-02-13 16:02:03 -07:00
  • fb96f5dfed bsd-user: Add sysarch syscall Stacey Son 2023-02-10 09:48:19 -07:00
  • a365689f20 build: Don't specify -no-pie for --static user-mode programs Warner Losh 2023-02-10 11:12:46 -07:00
  • 4cf41e8084 bsd-user: Don't truncate the return value from freebsd_syscall Doug Rabson 2022-12-10 08:38:04 +00:00
  • 9644e7142a tcg: Update docs/devel/tcg-ops.rst for temporary changes Richard Henderson 2023-01-30 10:26:25 -10:00
  • 438e685b1f tcg: Remove tcg_temp_local_new_*, tcg_const_local_* Richard Henderson 2023-01-29 14:48:55 -10:00
  • 383f50f753 exec/gen-icount: Don't use tcg_temp_local_new_i32 Richard Henderson 2023-01-29 14:47:48 -10:00
  • 177bbc81b5 target/xtensa: Don't use tcg_temp_local_new_* Richard Henderson 2023-01-29 14:45:57 -10:00
  • 9723281fbb target/ppc: Don't use tcg_temp_local_new Richard Henderson 2023-01-29 14:45:12 -10:00
  • 6180cc4027 target/mips: Don't use tcg_temp_local_new Richard Henderson 2023-01-29 14:44:25 -10:00
  • 3a5d177322 target/i386: Don't use tcg_temp_local_new Richard Henderson 2023-01-29 14:43:49 -10:00
  • e3eb3dab50 target/hppa: Don't use tcg_temp_local_new Richard Henderson 2023-01-29 14:42:26 -10:00
  • 839a0ff284 target/hexagon/idef-parser: Drop gen_tmp_local Richard Henderson 2023-02-26 16:01:00 -10:00
  • 7a819de850 target/hexagon: Don't use tcg_temp_local_new_* Richard Henderson 2023-01-29 14:41:33 -10:00
  • 5f153b12ab target/cris: Don't use tcg_temp_local_new Richard Henderson 2023-01-29 14:40:21 -10:00