 04f4915424
			
		
	
	
		04f4915424
		
	
	
	
	
		
			
			The M2Sxxx SoC family can only be used with Cortex-M3.
Propagating the CPU type from the board level is pointless.
Hard-code the CPU type at the SoC level.
Remove the now ignored MachineClass::default_cpu_type field.
Use the common code introduced in commit c9cf636d48 ("machine: Add
a valid_cpu_types property") to check for valid CPU type at the
board level.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20240129151828.59544-6-philmd@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
		
	
			
		
			
				
	
	
		
			74 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
			
		
		
	
	
			74 lines
		
	
	
		
			2.1 KiB
		
	
	
	
		
			C
		
	
	
	
	
	
| /*
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|  * Microsemi Smartfusion2 SoC
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|  *
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|  * Copyright (c) 2017 Subbaraya Sundeep <sundeep.lkml@gmail.com>
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|  *
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|  * Permission is hereby granted, free of charge, to any person obtaining a copy
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|  * of this software and associated documentation files (the "Software"), to deal
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|  * in the Software without restriction, including without limitation the rights
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|  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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|  * copies of the Software, and to permit persons to whom the Software is
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|  * furnished to do so, subject to the following conditions:
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|  *
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|  * The above copyright notice and this permission notice shall be included in
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|  * all copies or substantial portions of the Software.
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|  *
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|  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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|  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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|  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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|  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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|  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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|  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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|  * THE SOFTWARE.
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|  */
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| 
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| #ifndef HW_ARM_MSF2_SOC_H
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| #define HW_ARM_MSF2_SOC_H
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| 
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| #include "hw/arm/armv7m.h"
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| #include "hw/timer/mss-timer.h"
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| #include "hw/misc/msf2-sysreg.h"
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| #include "hw/ssi/mss-spi.h"
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| #include "hw/net/msf2-emac.h"
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| #include "hw/clock.h"
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| #include "qom/object.h"
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| 
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| #define TYPE_MSF2_SOC     "msf2-soc"
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| OBJECT_DECLARE_SIMPLE_TYPE(MSF2State, MSF2_SOC)
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| 
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| #define MSF2_NUM_SPIS         2
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| #define MSF2_NUM_UARTS        2
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| 
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| /*
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|  * System timer consists of two programmable 32-bit
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|  * decrementing counters that generate individual interrupts to
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|  * the Cortex-M3 processor
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|  */
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| #define MSF2_NUM_TIMERS       2
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| 
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| struct MSF2State {
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|     SysBusDevice parent_obj;
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| 
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|     ARMv7MState armv7m;
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| 
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|     char *part_name;
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|     uint64_t envm_size;
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|     uint64_t esram_size;
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| 
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|     Clock *m3clk;
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|     Clock *refclk;
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|     uint8_t apb0div;
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|     uint8_t apb1div;
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| 
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|     MSF2SysregState sysreg;
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|     MSSTimerState timer;
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|     MSSSpiState spi[MSF2_NUM_SPIS];
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|     MSF2EmacState emac;
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| 
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|     MemoryRegion nvm;
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|     MemoryRegion nvm_alias;
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|     MemoryRegion sram;
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| };
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| 
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| #endif
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